183 lines
5.9 KiB
ArmAsm
183 lines
5.9 KiB
ArmAsm
/* ------------------------------------------------------------------------- */
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/* */
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/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
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/* Copyright 2016-2019 NXP */
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/* All rights reserved. */
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/* */
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/* SPDX-License-Identifier: BSD-3-Clause */
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/*****************************************************************************/
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/* Version: GCC for ARM Embedded Processors */
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/*****************************************************************************/
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.syntax unified
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.arch armv7-m
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#include"flexram_config.s"
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/* Reset Handler */
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.thumb_func
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.align 2
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.globl Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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cpsid i /* Mask interrupts */
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.equ VTOR, 0xE000ED08
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ldr r0, =VTOR
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ldr r1, =__isr_vector
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str r1, [r0]
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ldr r2, [r1]
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msr msp, r2
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/* Reconfigure the memory map, which must match the setting of the linker script */
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dsb
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isb
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ldr r0, =__iomux_gpr17_adr /* load IOMUXC_GPR17 register address to R0 */
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ldr r1, =__iomux_gpr17_value /* move FlexRAM configuration value to R1 */
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str r1,[r0] /* store FLEXRAM configuration value to IOMUXC_GPR17 */
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dsb
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isb
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#if defined MIMXRT117x_SERIES
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ldr r0, =__iomux_gpr18_adr /* load IOMUXC_GPR18 register address to R0 */
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ldr r1, =__iomux_gpr18_value /* move FlexRAM configuration value to R1 */
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str r1,[r0] /* store FLEXRAM configuration value to IOMUXC_GPR18 */
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dsb
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isb
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#endif
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ldr r0, =__iomux_gpr16_adr /* load IOMUXC_GPR16 register address to R0 */
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ldr r1,[r0] /* load IOMUXC_GPR16 register value to R1 */
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orr r1, r1, #4 /* set corresponding FLEXRAM_BANK_CFG_SEL bit */
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str r1,[r0] /* store the value to IOMUXC_GPR16 (FLEXRAM_BANK_CFG_SEL = '1') */
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dsb
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isb
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#ifndef __NO_SYSTEM_INIT
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ldr r0,=SystemInit
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blx r0
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#endif
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/* Loop to copy data from read only memory to RAM. The ranges
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* of copy from/to are specified by following symbols evaluated in
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* linker script.
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* __etext: End of code section, i.e., begin of data sections to copy from.
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* __data_start__/__data_end__: RAM address range that data should be
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* __noncachedata_start__/__noncachedata_end__ : non-cacheable region
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* __ram_function_start__/__ram_function_end__ : ramfunction region
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* copied to. Both must be aligned to 4 bytes boundary. */
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ldr r1, =__etext
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ldr r2, =__data_start__
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ldr r3, =__data_end__
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#ifdef __PERFORMANCE_IMPLEMENTATION
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/* Here are two copies of loop implementations. First one favors performance
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* and the second one favors code size. Default uses the second one.
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* Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */
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subs r3, r2
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ble .LC1
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.LC0:
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subs r3, #4
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ldr r0, [r1, r3]
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str r0, [r2, r3]
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bgt .LC0
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.LC1:
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#else /* code size implementation */
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.LC0:
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cmp r2, r3
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ittt lt
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ldrlt r0, [r1], #4
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strlt r0, [r2], #4
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blt .LC0
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#endif
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#ifdef __STARTUP_INITIALIZE_RAMFUNCTION
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ldr r2, =__ram_function_start__
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ldr r3, =__ram_function_end__
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#ifdef __PERFORMANCE_IMPLEMENTATION
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/* Here are two copies of loop implementations. First one favors performance
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* and the second one favors code size. Default uses the second one.
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* Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */
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subs r3, r2
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ble .LC_ramfunc_copy_end
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.LC_ramfunc_copy_start:
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subs r3, #4
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ldr r0, [r1, r3]
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str r0, [r2, r3]
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bgt .LC_ramfunc_copy_start
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.LC_ramfunc_copy_end:
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#else /* code size implementation */
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.LC_ramfunc_copy_start:
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cmp r2, r3
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ittt lt
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ldrlt r0, [r1], #4
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strlt r0, [r2], #4
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blt .LC_ramfunc_copy_start
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#endif
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#endif /* __STARTUP_INITIALIZE_RAMFUNCTION */
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#ifdef __STARTUP_INITIALIZE_NONCACHEDATA
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ldr r2, =__noncachedata_start__
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ldr r3, =__noncachedata_init_end__
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#ifdef __PERFORMANCE_IMPLEMENTATION
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/* Here are two copies of loop implementations. First one favors performance
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* and the second one favors code size. Default uses the second one.
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* Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */
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subs r3, r2
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ble .LC3
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.LC2:
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subs r3, #4
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ldr r0, [r1, r3]
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str r0, [r2, r3]
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bgt .LC2
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.LC3:
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#else /* code size implementation */
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.LC2:
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cmp r2, r3
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ittt lt
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ldrlt r0, [r1], #4
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strlt r0, [r2], #4
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blt .LC2
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#endif
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/* zero inited ncache section initialization */
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ldr r3, =__noncachedata_end__
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movs r0,0
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.LC4:
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cmp r2,r3
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itt lt
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strlt r0,[r2],#4
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blt .LC4
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#endif /* __STARTUP_INITIALIZE_NONCACHEDATA */
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#ifdef __STARTUP_CLEAR_BSS
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/* This part of work usually is done in C library startup code. Otherwise,
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* define this macro to enable it in this startup.
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*
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* Loop to zero out BSS section, which uses following symbols
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* in linker script:
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* __bss_start__: start of BSS section. Must align to 4
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* __bss_end__: end of BSS section. Must align to 4
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*/
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ldr r1, =__bss_start__
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ldr r2, =__bss_end__
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movs r0, 0
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.LC5:
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cmp r1, r2
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itt lt
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strlt r0, [r1], #4
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blt .LC5
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#endif /* __STARTUP_CLEAR_BSS */
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cpsie i /* Unmask interrupts */
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#ifndef __START
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#define __START _start
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#endif
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#ifndef __ATOLLIC__
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ldr r0,=__START
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blx r0
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#else
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ldr r0,=__libc_init_array
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blx r0
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ldr r0,=main
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bx r0
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#endif
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.pool
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.size Reset_Handler, . - Reset_Handler
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