184 lines
6.3 KiB
C
184 lines
6.3 KiB
C
/*
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* This file is part of the OpenMV project.
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* Copyright (c) 2013/2014 Ibrahim Abdelkader <i.abdalkader@gmail.com>
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* This work is licensed under the MIT license, see the file LICENSE for details.
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*
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* SDRAM Driver.
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*
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*/
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#include <stdio.h>
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#include <stdbool.h>
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#include <stm32f4xx_hal.h>
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#include "mdefs.h"
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#include "pincfg.h"
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#include "systick.h"
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#include "sdram.h"
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#define SDRAM_TIMEOUT ((uint32_t)0xFFFF)
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#define REFRESH_COUNT ((uint32_t)0x0569) /* SDRAM refresh counter (90Mhz SD clock) */
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#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
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#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
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#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
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#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
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#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
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#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
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#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
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#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
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#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
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#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
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#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
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static SDRAM_HandleTypeDef hsdram;
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static FMC_SDRAM_TimingTypeDef SDRAM_Timing;
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static FMC_SDRAM_CommandTypeDef command;
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static void sdram_init_seq(SDRAM_HandleTypeDef
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*hsdram, FMC_SDRAM_CommandTypeDef *command);
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extern void __fatal_error(const char *msg);
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bool sdram_init()
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{
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/* SDRAM device configuration */
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hsdram.Instance = FMC_SDRAM_DEVICE;
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/* Timing configuration for 90 Mhz of SD clock frequency (180Mhz/2) */
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/* TMRD: 2 Clock cycles */
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SDRAM_Timing.LoadToActiveDelay = 2;
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/* TXSR: min=70ns (6x11.90ns) */
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SDRAM_Timing.ExitSelfRefreshDelay = 7;
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/* TRAS: min=45ns (4x11.90ns) max=120k (ns) */
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SDRAM_Timing.SelfRefreshTime = 7;
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/* TRC: min=67ns (6x11.90ns) */
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SDRAM_Timing.RowCycleDelay = 10;
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/* TWR: 2 Clock cycles */
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SDRAM_Timing.WriteRecoveryTime = 2;
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/* TRP: 20ns => 2x11.90ns */
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SDRAM_Timing.RPDelay = 3;
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/* TRCD: 20ns => 2x11.90ns */
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SDRAM_Timing.RCDDelay = 3;
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hsdram.Init.SDBank = FMC_SDRAM_BANK1;
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hsdram.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
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hsdram.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_10;
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hsdram.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_8;
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hsdram.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
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hsdram.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3;
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hsdram.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
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hsdram.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_3;
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hsdram.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
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hsdram.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_1;
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/* Initialize the SDRAM controller */
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if(HAL_SDRAM_Init(&hsdram, &SDRAM_Timing) != HAL_OK) {
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return false;
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}
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sdram_init_seq(&hsdram, &command);
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return true;
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}
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static void sdram_init_seq(SDRAM_HandleTypeDef
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*hsdram, FMC_SDRAM_CommandTypeDef *command)
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{
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/* Program the SDRAM external device */
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__IO uint32_t tmpmrd =0;
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/* Step 3: Configure a clock configuration enable command */
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command->CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
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command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
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command->AutoRefreshNumber = 1;
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command->ModeRegisterDefinition = 0;
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/* Send the command */
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HAL_SDRAM_SendCommand(hsdram, command, 0x1000);
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/* Step 4: Insert 100 ms delay */
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HAL_Delay(100);
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/* Step 5: Configure a PALL (precharge all) command */
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command->CommandMode = FMC_SDRAM_CMD_PALL;
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command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
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command->AutoRefreshNumber = 1;
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command->ModeRegisterDefinition = 0;
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/* Send the command */
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HAL_SDRAM_SendCommand(hsdram, command, 0x1000);
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/* Step 6 : Configure a Auto-Refresh command */
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command->CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
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command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
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command->AutoRefreshNumber = 4;
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command->ModeRegisterDefinition = 0;
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/* Send the command */
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HAL_SDRAM_SendCommand(hsdram, command, 0x1000);
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/* Step 7: Program the external memory mode register */
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tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 |
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SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
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SDRAM_MODEREG_CAS_LATENCY_3 |
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SDRAM_MODEREG_OPERATING_MODE_STANDARD |
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SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
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command->CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
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command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
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command->AutoRefreshNumber = 1;
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command->ModeRegisterDefinition = tmpmrd;
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/* Send the command */
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HAL_SDRAM_SendCommand(hsdram, command, 0x1000);
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/* Step 8: Set the refresh rate counter */
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/* (15.62 us x Freq) - 20 */
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/* Set the device refresh counter */
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HAL_SDRAM_ProgramRefreshRate(hsdram, REFRESH_COUNT);
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}
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bool DISABLE_OPT sdram_test()
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{
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uint8_t pattern = 0xAA;
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uint8_t antipattern = 0x55;
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uint32_t mem_size = (16*1024*1024);
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uint8_t * const mem_base = (uint8_t*)0xC0000000;
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printf("sdram test...\n");
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/* test data bus */
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for (uint8_t i=1; i; i<<=1) {
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*mem_base = i;
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if (*mem_base != i) {
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printf("data bus lines test failed! data (%d)\n", i);
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BREAK();
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}
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}
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/* test address bus */
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/* Check individual address lines */
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for (uint32_t i=1; i<mem_size; i<<=1) {
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mem_base[i] = pattern;
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if (mem_base[i] != pattern) {
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printf("address bus lines test failed! address (%p)\n", &mem_base[i]);
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BREAK();
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}
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}
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/* Check for aliasing (overlaping addresses) */
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mem_base[0] = antipattern;
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for (uint32_t i=1; i<mem_size; i<<=1) {
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if (mem_base[i] != pattern) {
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printf("address bus overlap %p\n", &mem_base[i]);
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BREAK();
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}
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}
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/* test all ram cells */
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for (uint32_t i=0; i<mem_size; i++) {
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mem_base[i] = pattern;
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if (mem_base[i] != pattern) {
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printf("address bus test failed! address (%p)\n", &mem_base[i]);
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BREAK();
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}
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}
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printf("sdram test passed\n");
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return true;
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}
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