199 lines
6.3 KiB
C
199 lines
6.3 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2018-2019 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "py/mphal.h"
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#include "powerctrl.h"
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static inline void powerctrl_config_systick(void) {
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// Configure SYSTICK to run at 1kHz (1ms interval)
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SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
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SysTick_Config(HAL_RCC_GetHCLKFreq() / 1000);
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NVIC_SetPriority(SysTick_IRQn, IRQ_PRI_SYSTICK);
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}
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#if defined(STM32F0)
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void SystemClock_Config(void) {
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// Enable power control peripheral
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__HAL_RCC_PWR_CLK_ENABLE();
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// Set flash latency to 1 because SYSCLK > 24MHz
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FLASH->ACR = (FLASH->ACR & ~0x7) | 0x1;
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#if MICROPY_HW_CLK_USE_HSI48
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// Use the 48MHz internal oscillator
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// HAL does not support RCC CFGR SW=3 (HSI48 direct to SYSCLK)
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// so use HSI48 -> PREDIV(divide by 2) -> PLL (mult by 2) -> SYSCLK.
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RCC->CR2 |= RCC_CR2_HSI48ON;
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while ((RCC->CR2 & RCC_CR2_HSI48RDY) == 0) {
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// Wait for HSI48 to be ready
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}
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RCC->CFGR = 0 << RCC_CFGR_PLLMUL_Pos | 3 << RCC_CFGR_PLLSRC_Pos; // PLL mult by 2, src = HSI48/PREDIV
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RCC->CFGR2 = 1; // Input clock divided by 2
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#elif MICROPY_HW_CLK_USE_HSE
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// Use HSE and the PLL to get a 48MHz SYSCLK
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#if MICROPY_HW_CLK_USE_BYPASS
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RCC->CR |= RCC_CR_HSEBYP;
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#endif
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RCC->CR |= RCC_CR_HSEON;
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while ((RCC->CR & RCC_CR_HSERDY) == 0) {
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// Wait for HSE to be ready
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}
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RCC->CFGR = ((48000000 / HSE_VALUE) - 2) << RCC_CFGR_PLLMUL_Pos | 2 << RCC_CFGR_PLLSRC_Pos;
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RCC->CFGR2 = 0; // Input clock not divided
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#elif MICROPY_HW_CLK_USE_HSI
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// Use the 8MHz internal oscillator and the PLL to get a 48MHz SYSCLK
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RCC->CR |= RCC_CR_HSION;
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while ((RCC->CR & RCC_CR_HSIRDY) == 0) {
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// Wait for HSI to be ready
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}
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RCC->CFGR = 4 << RCC_CFGR_PLLMUL_Pos | 1 << RCC_CFGR_PLLSRC_Pos; // PLL mult by 6, src = HSI
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RCC->CFGR2 = 0; // Input clock not divided
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#else
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#error System clock not specified
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#endif
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RCC->CR |= RCC_CR_PLLON; // Turn PLL on
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while ((RCC->CR & RCC_CR_PLLRDY) == 0) {
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// Wait for PLL to lock
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}
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const uint32_t sysclk_src = 2;
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// Select SYSCLK source
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RCC->CFGR |= sysclk_src << RCC_CFGR_SW_Pos;
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while (((RCC->CFGR >> RCC_CFGR_SWS_Pos) & 0x3) != sysclk_src) {
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// Wait for SYSCLK source to change
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}
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SystemCoreClockUpdate();
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powerctrl_config_systick();
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}
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#elif defined(STM32L0)
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void SystemClock_Config(void) {
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// Enable power control peripheral
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__HAL_RCC_PWR_CLK_ENABLE();
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// Set flash latency to 1 because SYSCLK > 16MHz
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FLASH->ACR |= FLASH_ACR_LATENCY;
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// Enable the 16MHz internal oscillator
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RCC->CR |= RCC_CR_HSION;
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while (!(RCC->CR & RCC_CR_HSIRDY)) {
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}
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// Use HSI16 and the PLL to get a 32MHz SYSCLK
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RCC->CFGR = 1 << RCC_CFGR_PLLDIV_Pos | 1 << RCC_CFGR_PLLMUL_Pos;
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR & RCC_CR_PLLRDY)) {
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// Wait for PLL to lock
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}
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const uint32_t sysclk_src = 3;
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// Select SYSCLK source
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RCC->CFGR |= sysclk_src << RCC_CFGR_SW_Pos;
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while (((RCC->CFGR >> RCC_CFGR_SWS_Pos) & 0x3) != sysclk_src) {
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// Wait for SYSCLK source to change
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}
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SystemCoreClockUpdate();
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powerctrl_config_systick();
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#if MICROPY_HW_ENABLE_RNG || MICROPY_HW_ENABLE_USB
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// Enable the 48MHz internal oscillator
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RCC->CRRCR |= RCC_CRRCR_HSI48ON;
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RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
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SYSCFG->CFGR3 |= SYSCFG_CFGR3_ENREF_HSI48;
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while (!(RCC->CRRCR & RCC_CRRCR_HSI48RDY)) {
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// Wait for HSI48 to be ready
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}
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// Select RC48 as HSI48 for USB and RNG
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RCC->CCIPR |= RCC_CCIPR_HSI48SEL;
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#if MICROPY_HW_ENABLE_USB
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// Synchronise HSI48 with 1kHz USB SoF
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__HAL_RCC_CRS_CLK_ENABLE();
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CRS->CR = 0x20 << CRS_CR_TRIM_Pos;
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CRS->CFGR = 2 << CRS_CFGR_SYNCSRC_Pos | 0x22 << CRS_CFGR_FELIM_Pos
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| __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000) << CRS_CFGR_RELOAD_Pos;
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#endif
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#endif
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}
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#elif defined(STM32WB)
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void SystemClock_Config(void) {
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// Enable the 32MHz external oscillator
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RCC->CR |= RCC_CR_HSEON;
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while (!(RCC->CR & RCC_CR_HSERDY)) {
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}
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// Use HSE and the PLL to get a 64MHz SYSCLK
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#define PLLM (HSE_VALUE / 8000000) // VCO input is 8MHz
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#define PLLN (24) // 24*8MHz = 192MHz
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#define PLLQ (4) // f_Q = 48MHz
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#define PLLR (3) // f_R = 64MHz
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RCC->PLLCFGR =
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(PLLR - 1) << RCC_PLLCFGR_PLLR_Pos | RCC_PLLCFGR_PLLREN
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| (PLLQ - 1) << RCC_PLLCFGR_PLLQ_Pos | RCC_PLLCFGR_PLLQEN
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| PLLN << RCC_PLLCFGR_PLLN_Pos
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| (PLLM - 1) << RCC_PLLCFGR_PLLM_Pos
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| 3 << RCC_PLLCFGR_PLLSRC_Pos;
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR & RCC_CR_PLLRDY)) {
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// Wait for PLL to lock
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}
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const uint32_t sysclk_src = 3;
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// Set divider for HCLK2 to 2 so f_HCLK2 = 32MHz
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RCC->EXTCFGR = 8 << RCC_EXTCFGR_C2HPRE_Pos;
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// Set flash latency to 3 because SYSCLK > 54MHz
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FLASH->ACR |= 3 << FLASH_ACR_LATENCY_Pos;
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// Select SYSCLK source
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RCC->CFGR |= sysclk_src << RCC_CFGR_SW_Pos;
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while (((RCC->CFGR >> RCC_CFGR_SWS_Pos) & 0x3) != sysclk_src) {
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// Wait for SYSCLK source to change
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}
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// Select PLLQ as 48MHz source for USB and RNG
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RCC->CCIPR = 2 << RCC_CCIPR_CLK48SEL_Pos;
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SystemCoreClockUpdate();
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powerctrl_config_systick();
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}
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#endif
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