340 lines
19 KiB
C
340 lines
19 KiB
C
//*****************************************************************************
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//
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// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//*****************************************************************************
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#ifndef __HW_DES_H__
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#define __HW_DES_H__
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//*****************************************************************************
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//
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// The following are defines for the DES_P register offsets.
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//
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//*****************************************************************************
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#define DES_O_KEY3_L 0x00000000 // KEY3 (LSW) for 192-bit key
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#define DES_O_KEY3_H 0x00000004 // KEY3 (MSW) for 192-bit key
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#define DES_O_KEY2_L 0x00000008 // KEY2 (LSW) for 192-bit key
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#define DES_O_KEY2_H 0x0000000C // KEY2 (MSW) for 192-bit key
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#define DES_O_KEY1_L 0x00000010 // KEY1 (LSW) for 128-bit
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// key/192-bit key
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#define DES_O_KEY1_H 0x00000014 // KEY1 (LSW) for 128-bit
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// key/192-bit key
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#define DES_O_IV_L 0x00000018 // Initialization vector LSW
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#define DES_O_IV_H 0x0000001C // Initialization vector MSW
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#define DES_O_CTRL 0x00000020
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#define DES_O_LENGTH 0x00000024 // Indicates the cryptographic data
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// length in bytes for all modes.
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// Once processing is started with
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// this context this length
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// decrements to zero. Data lengths
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// up to (2^32 – 1) bytes are
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// allowed. A write to this register
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// triggers the engine to start
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// using this context. For a Host
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// read operation these registers
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// return all-zeroes.
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#define DES_O_DATA_L 0x00000028 // Data register(LSW) to read/write
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// encrypted/decrypted data.
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#define DES_O_DATA_H 0x0000002C // Data register(MSW) to read/write
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// encrypted/decrypted data.
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#define DES_O_REVISION 0x00000030
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#define DES_O_SYSCONFIG 0x00000034
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#define DES_O_SYSSTATUS 0x00000038
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#define DES_O_IRQSTATUS 0x0000003C // This register indicates the
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// interrupt status. If one of the
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// interrupt bits is set the
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// interrupt output will be asserted
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#define DES_O_IRQENABLE 0x00000040 // This register contains an enable
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// bit for each unique interrupt
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// generated by the module. It
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// matches the layout of
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// DES_IRQSTATUS register. An
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// interrupt is enabled when the bit
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// in this register is set to 1
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//******************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_KEY3_L register.
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//
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//******************************************************************************
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#define DES_KEY3_L_KEY3_L_M 0xFFFFFFFF // data for key3
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#define DES_KEY3_L_KEY3_L_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_KEY3_H register.
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//
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//******************************************************************************
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#define DES_KEY3_H_KEY3_H_M 0xFFFFFFFF // data for key3
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#define DES_KEY3_H_KEY3_H_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_KEY2_L register.
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//
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//******************************************************************************
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#define DES_KEY2_L_KEY2_L_M 0xFFFFFFFF // data for key2
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#define DES_KEY2_L_KEY2_L_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_KEY2_H register.
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//
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//******************************************************************************
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#define DES_KEY2_H_KEY2_H_M 0xFFFFFFFF // data for key2
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#define DES_KEY2_H_KEY2_H_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_KEY1_L register.
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//
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//******************************************************************************
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#define DES_KEY1_L_KEY1_L_M 0xFFFFFFFF // data for key1
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#define DES_KEY1_L_KEY1_L_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_KEY1_H register.
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//
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//******************************************************************************
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#define DES_KEY1_H_KEY1_H_M 0xFFFFFFFF // data for key1
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#define DES_KEY1_H_KEY1_H_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_IV_L register.
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//
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//******************************************************************************
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#define DES_IV_L_IV_L_M 0xFFFFFFFF // initialization vector for CBC
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// CFB modes
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#define DES_IV_L_IV_L_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_IV_H register.
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//
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//******************************************************************************
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#define DES_IV_H_IV_H_M 0xFFFFFFFF // initialization vector for CBC
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// CFB modes
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#define DES_IV_H_IV_H_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_CTRL register.
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//
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//******************************************************************************
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#define DES_CTRL_CONTEXT 0x80000000 // If ‘1’ this read-only status bit
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// indicates that the context data
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// registers can be overwritten and
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// the host is permitted to write
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// the next context.
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#define DES_CTRL_MODE_M 0x00000030 // Select CBC ECB or CFB mode 0x0
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// ecb mode 0x1 cbc mode 0x2 cfb
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// mode 0x3 reserved
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#define DES_CTRL_MODE_S 4
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#define DES_CTRL_TDES 0x00000008 // Select DES or triple DES
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// encryption/decryption. 0 des mode
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// 1 tdes mode
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#define DES_CTRL_DIRECTION 0x00000004 // select encryption/decryption 0
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// decryption is selected 1
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// Encryption is selected
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#define DES_CTRL_INPUT_READY 0x00000002 // When '1' ready to
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// encrypt/decrypt data
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#define DES_CTRL_OUTPUT_READY 0x00000001 // When '1' Data
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// decrypted/encrypted ready
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//******************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_LENGTH register.
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//
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//******************************************************************************
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#define DES_LENGTH_LENGTH_M 0xFFFFFFFF
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#define DES_LENGTH_LENGTH_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_DATA_L register.
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//
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//******************************************************************************
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#define DES_DATA_L_DATA_L_M 0xFFFFFFFF // data for encryption/decryption
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#define DES_DATA_L_DATA_L_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_DATA_H register.
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//
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//******************************************************************************
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#define DES_DATA_H_DATA_H_M 0xFFFFFFFF // data for encryption/decryption
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#define DES_DATA_H_DATA_H_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_REVISION register.
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//
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//******************************************************************************
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#define DES_REVISION_SCHEME_M 0xC0000000
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#define DES_REVISION_SCHEME_S 30
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#define DES_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software
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// compatible module family. If
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// there is no level of software
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// compatibility a new Func number
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// (and hence REVISION) should be
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// assigned.
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#define DES_REVISION_FUNC_S 16
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#define DES_REVISION_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP
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// design owner. RTL follows a
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// numbering such as X.Y.R.Z which
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// are explained in this table. R
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// changes ONLY when: (1) PDS
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// uploads occur which may have been
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// due to spec changes (2) Bug fixes
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// occur (3) Resets to '0' when X or
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// Y changes. Design team has an
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// internal 'Z' (customer invisible)
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// number which increments on every
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// drop that happens due to DV and
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// RTL updates. Z resets to 0 when R
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// increments.
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#define DES_REVISION_R_RTL_S 11
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#define DES_REVISION_X_MAJOR_M \
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0x00000700 // Major Revision (X) maintained by
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// IP specification owner. X changes
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// ONLY when: (1) There is a major
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// feature addition. An example
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// would be adding Master Mode to
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// Utopia Level2. The Func field (or
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// Class/Type in old PID format)
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// will remain the same. X does NOT
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// change due to: (1) Bug fixes (2)
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// Change in feature parameters.
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#define DES_REVISION_X_MAJOR_S 8
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#define DES_REVISION_CUSTOM_M 0x000000C0
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#define DES_REVISION_CUSTOM_S 6
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#define DES_REVISION_Y_MINOR_M \
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0x0000003F // Minor Revision (Y) maintained by
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// IP specification owner. Y changes
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// ONLY when: (1) Features are
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// scaled (up or down). Flexibility
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// exists in that this feature
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// scalability may either be
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// represented in the Y change or a
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// specific register in the IP that
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// indicates which features are
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// exactly available. (2) When
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// feature creeps from Is-Not list
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// to Is list. But this may not be
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// the case once it sees silicon; in
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// which case X will change. Y does
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// NOT change due to: (1) Bug fixes
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// (2) Typos or clarifications (3)
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// major functional/feature
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// change/addition/deletion. Instead
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// these changes may be reflected
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// via R S X as applicable. Spec
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// owner maintains a
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// customer-invisible number 'S'
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// which changes due to: (1)
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// Typos/clarifications (2) Bug
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// documentation. Note that this bug
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// is not due to a spec change but
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// due to implementation.
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// Nevertheless the spec tracks the
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// IP bugs. An RTL release (say for
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// silicon PG1.1) that occurs due to
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// bug fix should document the
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// corresponding spec number (X.Y.S)
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// in its release notes.
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#define DES_REVISION_Y_MINOR_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_SYSCONFIG register.
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//
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//******************************************************************************
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#define DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \
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0x00000080 // If set to ‘1’ the DMA context
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// request is enabled. 0 Dma
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// disabled 1 Dma enabled
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#define DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \
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0x00000040 // If set to ‘1’ the DMA output
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// request is enabled. 0 Dma
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// disabled 1 Dma enabled
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#define DES_SYSCONFIG_DMA_REQ_DATA_IN_EN \
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0x00000020 // If set to ‘1’ the DMA input
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// request is enabled. 0 Dma
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// disabled 1 Dma enabled
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//******************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_SYSSTATUS register.
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//
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//******************************************************************************
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#define DES_SYSSTATUS_RESETDONE \
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0x00000001
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//******************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_IRQSTATUS register.
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//
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//******************************************************************************
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#define DES_IRQSTATUS_DATA_OUT \
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0x00000004 // This bit indicates data output
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// interrupt is active and triggers
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// the interrupt output.
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#define DES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input
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// interrupt is active and triggers
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// the interrupt output.
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#define DES_IRQSTATUS_CONTEX_IN \
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0x00000001 // This bit indicates context
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// interrupt is active and triggers
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// the interrupt output.
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//******************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_IRQENABLE register.
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//
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//******************************************************************************
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#define DES_IRQENABLE_M_DATA_OUT \
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0x00000004 // If this bit is set to ‘1’ the
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// secure data output interrupt is
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// enabled.
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#define DES_IRQENABLE_M_DATA_IN \
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0x00000002 // If this bit is set to ‘1’ the
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// secure data input interrupt is
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// enabled.
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#define DES_IRQENABLE_M_CONTEX_IN \
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0x00000001 // If this bit is set to ‘1’ the
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// secure context interrupt is
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// enabled.
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#endif // __HW_DES_H__
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