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micropython/stmhal/cmsis/stm32f767xx.h

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/**
******************************************************************************
* @file stm32f767xx.h
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/** @addtogroup CMSIS_Device
* @{
*/
/** @addtogroup stm32f767xx
* @{
*/
#ifndef __STM32F767xx_H
#define __STM32F767xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
/**
* @brief STM32F7xx Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum
{
/****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */
/****** STM32 specific Interrupt Numbers **********************************************************************/
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
FLASH_IRQn = 4, /*!< FLASH global Interrupt */
RCC_IRQn = 5, /*!< RCC global Interrupt */
EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
USART1_IRQn = 37, /*!< USART1 global Interrupt */
USART2_IRQn = 38, /*!< USART2 global Interrupt */
USART3_IRQn = 39, /*!< USART3 global Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
FMC_IRQn = 48, /*!< FMC global Interrupt */
SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
UART4_IRQn = 52, /*!< UART4 global Interrupt */
UART5_IRQn = 53, /*!< UART5 global Interrupt */
TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
TIM7_IRQn = 55, /*!< TIM7 global interrupt */
DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
ETH_IRQn = 61, /*!< Ethernet global Interrupt */
ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
USART6_IRQn = 71, /*!< USART6 global interrupt */
I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
DCMI_IRQn = 78, /*!< DCMI global interrupt */
RNG_IRQn = 80, /*!< RNG global interrupt */
FPU_IRQn = 81, /*!< FPU global interrupt */
UART7_IRQn = 82, /*!< UART7 global interrupt */
UART8_IRQn = 83, /*!< UART8 global interrupt */
SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
LTDC_IRQn = 88, /*!< LTDC global Interrupt */
LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
DFSDM1_FLT0_IRQn = 99, /*!< DFSDM1 Filter 0 global Interrupt */
DFSDM1_FLT1_IRQn = 100, /*!< DFSDM1 Filter 1 global Interrupt */
DFSDM1_FLT2_IRQn = 101, /*!< DFSDM1 Filter 2 global Interrupt */
DFSDM1_FLT3_IRQn = 102, /*!< DFSDM1 Filter 3 global Interrupt */
SDMMC2_IRQn = 103, /*!< SDMMC2 global Interrupt */
CAN3_TX_IRQn = 104, /*!< CAN3 TX Interrupt */
CAN3_RX0_IRQn = 105, /*!< CAN3 RX0 Interrupt */
CAN3_RX1_IRQn = 106, /*!< CAN3 RX1 Interrupt */
CAN3_SCE_IRQn = 107, /*!< CAN3 SCE Interrupt */
JPEG_IRQn = 108, /*!< JPEG global Interrupt */
MDIOS_IRQn = 109 /*!< MDIO Slave global Interrupt */
} IRQn_Type;
/**
* @}
*/
/**
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
*/
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
#include "system_stm32f7xx.h"
#include <stdint.h>
/** @addtogroup Peripheral_registers_structures
* @{
*/
/**
* @brief Analog to Digital Converter
*/
typedef struct
{
__IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
__IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
__IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
__IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
__IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
__IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
__IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
__IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
__IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
__IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
__IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
__IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
__IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
__IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
__IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
__IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
__IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
__IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
__IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
__IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
} ADC_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
__IO uint32_t CDR; /*!< ADC common regular data register for dual
AND triple modes, Address offset: ADC1 base address + 0x308 */
} ADC_Common_TypeDef;
/**
* @brief Controller Area Network TxMailBox
*/
typedef struct
{
__IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
__IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
__IO uint32_t TDLR; /*!< CAN mailbox data low register */
__IO uint32_t TDHR; /*!< CAN mailbox data high register */
} CAN_TxMailBox_TypeDef;
/**
* @brief Controller Area Network FIFOMailBox
*/
typedef struct
{
__IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
__IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
__IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
__IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
} CAN_FIFOMailBox_TypeDef;
/**
* @brief Controller Area Network FilterRegister
*/
typedef struct
{
__IO uint32_t FR1; /*!< CAN Filter bank register 1 */
__IO uint32_t FR2; /*!< CAN Filter bank register 1 */
} CAN_FilterRegister_TypeDef;
/**
* @brief Controller Area Network
*/
typedef struct
{
__IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
__IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
__IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
__IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
__IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
__IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
__IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
__IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
__IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
__IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
uint32_t RESERVED2; /*!< Reserved, 0x208 */
__IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
uint32_t RESERVED3; /*!< Reserved, 0x210 */
__IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
uint32_t RESERVED4; /*!< Reserved, 0x218 */
__IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
} CAN_TypeDef;
/**
* @brief HDMI-CEC
*/
typedef struct
{
__IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
__IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
__IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
__IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
__IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
__IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
}CEC_TypeDef;
/**
* @brief CRC calculation unit
*/
typedef struct
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
uint8_t RESERVED0; /*!< Reserved, 0x05 */
uint16_t RESERVED1; /*!< Reserved, 0x06 */
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
uint32_t RESERVED2; /*!< Reserved, 0x0C */
__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
} CRC_TypeDef;
/**
* @brief Digital to Analog Converter
*/
typedef struct
{
__IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
__IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
__IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
__IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
} DAC_TypeDef;
/**
* @brief DFSDM module registers
*/
typedef struct
{
__IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
__IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
__IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
__IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
__IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
__IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
__IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
__IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
__IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
__IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
__IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
__IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
__IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
__IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
__IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
} DFSDM_Filter_TypeDef;
/**
* @brief DFSDM channel configuration registers
*/
typedef struct
{
__IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
__IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
__IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
short circuit detector register, Address offset: 0x08 */
__IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
__IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
} DFSDM_Channel_TypeDef;
/**
* @brief Debug MCU
*/
typedef struct
{
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
__IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
}DBGMCU_TypeDef;
/**
* @brief DCMI
*/
typedef struct
{
__IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
__IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
__IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
__IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
__IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
__IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
__IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
__IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
__IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
__IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
__IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
} DCMI_TypeDef;
/**
* @brief DMA Controller
*/
typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;
typedef struct
{
__IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
__IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
__IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
__IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
} DMA_TypeDef;
/**
* @brief DMA2D Controller
*/
typedef struct
{
__IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
__IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
__IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
__IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
__IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
__IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
__IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
__IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
__IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
__IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
__IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
__IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
__IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
__IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
__IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
__IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
__IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
__IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
__IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
__IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
__IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
__IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
} DMA2D_TypeDef;
/**
* @brief Ethernet MAC
*/
typedef struct
{
__IO uint32_t MACCR;
__IO uint32_t MACFFR;
__IO uint32_t MACHTHR;
__IO uint32_t MACHTLR;
__IO uint32_t MACMIIAR;
__IO uint32_t MACMIIDR;
__IO uint32_t MACFCR;
__IO uint32_t MACVLANTR; /* 8 */
uint32_t RESERVED0[2];
__IO uint32_t MACRWUFFR; /* 11 */
__IO uint32_t MACPMTCSR;
uint32_t RESERVED1[2];
__IO uint32_t MACSR; /* 15 */
__IO uint32_t MACIMR;
__IO uint32_t MACA0HR;
__IO uint32_t MACA0LR;
__IO uint32_t MACA1HR;
__IO uint32_t MACA1LR;
__IO uint32_t MACA2HR;
__IO uint32_t MACA2LR;
__IO uint32_t MACA3HR;
__IO uint32_t MACA3LR; /* 24 */
uint32_t RESERVED2[40];
__IO uint32_t MMCCR; /* 65 */
__IO uint32_t MMCRIR;
__IO uint32_t MMCTIR;
__IO uint32_t MMCRIMR;
__IO uint32_t MMCTIMR; /* 69 */
uint32_t RESERVED3[14];
__IO uint32_t MMCTGFSCCR; /* 84 */
__IO uint32_t MMCTGFMSCCR;
uint32_t RESERVED4[5];
__IO uint32_t MMCTGFCR;
uint32_t RESERVED5[10];
__IO uint32_t MMCRFCECR;
__IO uint32_t MMCRFAECR;
uint32_t RESERVED6[10];
__IO uint32_t MMCRGUFCR;
uint32_t RESERVED7[334];
__IO uint32_t PTPTSCR;
__IO uint32_t PTPSSIR;
__IO uint32_t PTPTSHR;
__IO uint32_t PTPTSLR;
__IO uint32_t PTPTSHUR;
__IO uint32_t PTPTSLUR;
__IO uint32_t PTPTSAR;
__IO uint32_t PTPTTHR;
__IO uint32_t PTPTTLR;
__IO uint32_t RESERVED8;
__IO uint32_t PTPTSSR;
uint32_t RESERVED9[565];
__IO uint32_t DMABMR;
__IO uint32_t DMATPDR;
__IO uint32_t DMARPDR;
__IO uint32_t DMARDLAR;
__IO uint32_t DMATDLAR;
__IO uint32_t DMASR;
__IO uint32_t DMAOMR;
__IO uint32_t DMAIER;
__IO uint32_t DMAMFBOCR;
__IO uint32_t DMARSWTR;
uint32_t RESERVED10[8];
__IO uint32_t DMACHTDR;
__IO uint32_t DMACHRDR;
__IO uint32_t DMACHTBAR;
__IO uint32_t DMACHRBAR;
} ETH_TypeDef;
/**
* @brief External Interrupt/Event Controller
*/
typedef struct
{
__IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
__IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
__IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
__IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
__IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
__IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
} EXTI_TypeDef;
/**
* @brief FLASH Registers
*/
typedef struct
{
__IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
__IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
__IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
__IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
__IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
__IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
__IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */
} FLASH_TypeDef;
/**
* @brief Flexible Memory Controller
*/
typedef struct
{
__IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
} FMC_Bank1_TypeDef;
/**
* @brief Flexible Memory Controller Bank1E
*/
typedef struct
{
__IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
} FMC_Bank1E_TypeDef;
/**
* @brief Flexible Memory Controller Bank3
*/
typedef struct
{
__IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
__IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
__IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
__IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
uint32_t RESERVED0; /*!< Reserved, 0x90 */
__IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
} FMC_Bank3_TypeDef;
/**
* @brief Flexible Memory Controller Bank5_6
*/
typedef struct
{
__IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
__IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
__IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
__IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
__IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
} FMC_Bank5_6_TypeDef;
/**
* @brief General Purpose I/O
*/
typedef struct
{
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
__IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef;
/**
* @brief System configuration controller
*/
typedef struct
{
__IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
__IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
uint32_t RESERVED; /*!< Reserved, 0x18 */
__IO uint32_t CBR; /*!< SYSCFG Class B register, Address offset: 0x1C */
__IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
} SYSCFG_TypeDef;
/**
* @brief Inter-integrated Circuit Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
__IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
__IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
__IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
__IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
__IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
__IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
__IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
__IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
__IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
} I2C_TypeDef;
/**
* @brief Independent WATCHDOG
*/
typedef struct
{
__IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
__IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
__IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
__IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
__IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
} IWDG_TypeDef;
/**
* @brief LCD-TFT Display Controller
*/
typedef struct
{
uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
__IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
__IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
__IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
__IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
__IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
__IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
__IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
__IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
__IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
__IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
__IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
__IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
__IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
} LTDC_TypeDef;
/**
* @brief LCD-TFT Display layer x Controller
*/
typedef struct
{
__IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
__IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
__IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
__IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
__IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
__IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
__IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
__IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
uint32_t RESERVED0[2]; /*!< Reserved */
__IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
__IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
__IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
uint32_t RESERVED1[3]; /*!< Reserved */
__IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
} LTDC_Layer_TypeDef;
/**
* @brief Power Control
*/
typedef struct
{
__IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
__IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */
__IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
__IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */
} PWR_TypeDef;
/**
* @brief Reset and Clock Control
*/
typedef struct
{
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
__IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
__IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
__IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
__IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
__IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
__IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
uint32_t RESERVED0; /*!< Reserved, 0x1C */
__IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
__IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
__IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
__IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
__IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
uint32_t RESERVED2; /*!< Reserved, 0x3C */
__IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
__IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
__IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
__IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
uint32_t RESERVED4; /*!< Reserved, 0x5C */
__IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
__IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
__IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
__IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
__IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
__IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
__IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
__IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */
__IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */
} RCC_TypeDef;
/**
* @brief Real-Time Clock
*/
typedef struct
{
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
__IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
__IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
__IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
__IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
__IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
uint32_t reserved; /*!< Reserved */
__IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
__IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
__IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
__IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
__IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
__IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
__IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
__IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
__IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
__IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
__IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
__IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
__IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
__IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
__IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
__IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
__IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
__IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
__IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
__IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
__IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
__IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
__IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
__IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
__IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
__IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
__IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
__IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
__IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
__IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
__IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
__IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
__IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
__IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
__IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
__IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
__IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
__IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
__IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
__IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
__IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
__IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
__IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
__IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
} RTC_TypeDef;
/**
* @brief Serial Audio Interface
*/
typedef struct
{
__IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
} SAI_TypeDef;
typedef struct
{
__IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
__IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
__IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
__IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
__IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
__IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
__IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
__IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
} SAI_Block_TypeDef;
/**
* @brief SPDIF-RX Interface
*/
typedef struct
{
__IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
__IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
__IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
__IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
__IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
__IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
__IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
} SPDIFRX_TypeDef;
/**
* @brief SD host Interface
*/
typedef struct
{
__IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
__IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */
__IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
__IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
__I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
__I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
__I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
__I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
__I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
__IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
__IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
__IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
__I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
__I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
__IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
__IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
__I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
__IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
} SDMMC_TypeDef;
/**
* @brief Serial Peripheral Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
__IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
__IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
} SPI_TypeDef;
/**
* @brief QUAD Serial Peripheral Interface
*/
typedef struct
{
__IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
__IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
__IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
__IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
__IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
__IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
__IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
__IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
__IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
__IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
__IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
__IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
} QUADSPI_TypeDef;
/**
* @brief TIM
*/
typedef struct
{
__IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
__IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
__IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
__IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
__IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
__IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
__IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
__IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
__IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
__IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
__IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
__IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
__IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
__IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
__IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */
__IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */
__IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */
__IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */
} TIM_TypeDef;
/**
* @brief LPTIMIMER
*/
typedef struct
{
__IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
__IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
__IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
__IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
__IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
__IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
__IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
__IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
} LPTIM_TypeDef;
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/
typedef struct
{
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
__IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
__IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
__IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
__IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
__IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
} USART_TypeDef;
/**
* @brief Window WATCHDOG
*/
typedef struct
{
__IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
__IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
} WWDG_TypeDef;
/**
* @brief RNG
*/
typedef struct
{
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
} RNG_TypeDef;
/**
* @}
*/
/**
* @brief USB_OTG_Core_Registers
*/
typedef struct
{
__IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
__IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
__IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
__IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
__IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
__IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
__IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
__IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
__IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
__IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
__IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
__IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
uint32_t Reserved30[2]; /*!< Reserved 030h */
__IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
__IO uint32_t CID; /*!< User ID Register 03Ch */
uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
__IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
uint32_t Reserved6; /*!< Reserved 050h */
__IO uint32_t GLPMCFG; /*!< LPM Register 054h */
__IO uint32_t GPWRDN; /*!< Power Down Register 058h */
__IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
__IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
__IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
__IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
} USB_OTG_GlobalTypeDef;
/**
* @brief USB_OTG_device_Registers
*/
typedef struct
{
__IO uint32_t DCFG; /*!< dev Configuration Register 800h */
__IO uint32_t DCTL; /*!< dev Control Register 804h */
__IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
uint32_t Reserved0C; /*!< Reserved 80Ch */
__IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
__IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
__IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
__IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
uint32_t Reserved20; /*!< Reserved 820h */
uint32_t Reserved9; /*!< Reserved 824h */
__IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
__IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
__IO uint32_t DTHRCTL; /*!< dev threshold 830h */
__IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
__IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
__IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
uint32_t Reserved40; /*!< dedicated EP mask 840h */
__IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
__IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
} USB_OTG_DeviceTypeDef;
/**
* @brief USB_OTG_IN_Endpoint-Specific_Register
*/
typedef struct
{
__IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
__IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
__IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
__IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
__IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
} USB_OTG_INEndpointTypeDef;
/**
* @brief USB_OTG_OUT_Endpoint-Specific_Registers
*/
typedef struct
{
__IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
__IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
__IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
__IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
} USB_OTG_OUTEndpointTypeDef;
/**
* @brief USB_OTG_Host_Mode_Register_Structures
*/
typedef struct
{
__IO uint32_t HCFG; /*!< Host Configuration Register 400h */
__IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
__IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
uint32_t Reserved40C; /*!< Reserved 40Ch */
__IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
__IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
__IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
} USB_OTG_HostTypeDef;
/**
* @brief USB_OTG_Host_Channel_Specific_Registers
*/
typedef struct
{
__IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
__IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
__IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
__IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
__IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
__IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
uint32_t Reserved[2]; /*!< Reserved */
} USB_OTG_HostChannelTypeDef;
/**
* @}
*/
/**
* @brief JPEG Codec
*/
typedef struct
{
__IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
__IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
__IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
__IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
__IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
__IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
__IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
__IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
__IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
__IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
__IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
__IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
__IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
__IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
__IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
__IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
__IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
__IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
__IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
__IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
__IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
__IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encoder, AC Huffman table 0, Address offset: 500h-65Ch */
__IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encoder, AC Huffman table 1, Address offset: 660h-7BCh */
__IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encoder, DC Huffman table 0, Address offset: 7C0h-7DCh */
__IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encoder, DC Huffman table 1, Address offset: 7E0h-7FCh */
} JPEG_TypeDef;
/**
* @brief MDIOS
*/
typedef struct
{
__IO uint32_t CR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 00h */
__IO uint32_t WRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 04h */
__IO uint32_t CWRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 08h */
__IO uint32_t RDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 0Ch */
__IO uint32_t CRDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 10h */
__IO uint32_t SR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 14h */
__IO uint32_t CLRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 18h */
uint32_t RESERVED0[57]; /* Reserved Address offset: 1Ch */
__IO uint32_t DINR0; /*!< MDIOS Input Data Register (MDIOS_DINR0), Address offset: 100h */
__IO uint32_t DINR1; /*!< MDIOS Input Data Register (MDIOS_DINR1), Address offset: 104h */
__IO uint32_t DINR2; /*!< MDIOS Input Data Register (MDIOS_DINR2), Address offset: 108h */
__IO uint32_t DINR3; /*!< MDIOS Input Data Register (MDIOS_DINR3), Address offset: 10Ch */
__IO uint32_t DINR4; /*!< MDIOS Input Data Register (MDIOS_DINR4), Address offset: 110h */
__IO uint32_t DINR5; /*!< MDIOS Input Data Register (MDIOS_DINR5), Address offset: 114h */
__IO uint32_t DINR6; /*!< MDIOS Input Data Register (MDIOS_DINR6), Address offset: 118h */
__IO uint32_t DINR7; /*!< MDIOS Input Data Register (MDIOS_DINR7), Address offset: 11Ch */
__IO uint32_t DINR8; /*!< MDIOS Input Data Register (MDIOS_DINR8), Address offset: 120h */
__IO uint32_t DINR9; /*!< MDIOS Input Data Register (MDIOS_DINR9), Address offset: 124h */
__IO uint32_t DINR10; /*!< MDIOS Input Data Register (MDIOS_DINR10), Address offset: 128h */
__IO uint32_t DINR11; /*!< MDIOS Input Data Register (MDIOS_DINR11), Address offset: 12Ch */
__IO uint32_t DINR12; /*!< MDIOS Input Data Register (MDIOS_DINR12), Address offset: 130h */
__IO uint32_t DINR13; /*!< MDIOS Input Data Register (MDIOS_DINR13), Address offset: 134h */
__IO uint32_t DINR14; /*!< MDIOS Input Data Register (MDIOS_DINR14), Address offset: 138h */
__IO uint32_t DINR15; /*!< MDIOS Input Data Register (MDIOS_DINR15), Address offset: 13Ch */
__IO uint32_t DINR16; /*!< MDIOS Input Data Register (MDIOS_DINR16), Address offset: 140h */
__IO uint32_t DINR17; /*!< MDIOS Input Data Register (MDIOS_DINR17), Address offset: 144h */
__IO uint32_t DINR18; /*!< MDIOS Input Data Register (MDIOS_DINR18), Address offset: 148h */
__IO uint32_t DINR19; /*!< MDIOS Input Data Register (MDIOS_DINR19), Address offset: 14Ch */
__IO uint32_t DINR20; /*!< MDIOS Input Data Register (MDIOS_DINR20), Address offset: 150h */
__IO uint32_t DINR21; /*!< MDIOS Input Data Register (MDIOS_DINR21), Address offset: 154h */
__IO uint32_t DINR22; /*!< MDIOS Input Data Register (MDIOS_DINR22), Address offset: 158h */
__IO uint32_t DINR23; /*!< MDIOS Input Data Register (MDIOS_DINR23), Address offset: 15Ch */
__IO uint32_t DINR24; /*!< MDIOS Input Data Register (MDIOS_DINR24), Address offset: 160h */
__IO uint32_t DINR25; /*!< MDIOS Input Data Register (MDIOS_DINR25), Address offset: 164h */
__IO uint32_t DINR26; /*!< MDIOS Input Data Register (MDIOS_DINR26), Address offset: 168h */
__IO uint32_t DINR27; /*!< MDIOS Input Data Register (MDIOS_DINR27), Address offset: 16Ch */
__IO uint32_t DINR28; /*!< MDIOS Input Data Register (MDIOS_DINR28), Address offset: 170h */
__IO uint32_t DINR29; /*!< MDIOS Input Data Register (MDIOS_DINR29), Address offset: 174h */
__IO uint32_t DINR30; /*!< MDIOS Input Data Register (MDIOS_DINR30), Address offset: 178h */
__IO uint32_t DINR31; /*!< MDIOS Input Data Register (MDIOS_DINR31), Address offset: 17Ch */
__IO uint32_t DOUTR0; /*!< MDIOS Output Data Register (MDIOS_DOUTR0), Address offset: 180h */
__IO uint32_t DOUTR1; /*!< MDIOS Output Data Register (MDIOS_DOUTR1), Address offset: 184h */
__IO uint32_t DOUTR2; /*!< MDIOS Output Data Register (MDIOS_DOUTR2), Address offset: 188h */
__IO uint32_t DOUTR3; /*!< MDIOS Output Data Register (MDIOS_DOUTR3), Address offset: 18Ch */
__IO uint32_t DOUTR4; /*!< MDIOS Output Data Register (MDIOS_DOUTR4), Address offset: 190h */
__IO uint32_t DOUTR5; /*!< MDIOS Output Data Register (MDIOS_DOUTR5), Address offset: 194h */
__IO uint32_t DOUTR6; /*!< MDIOS Output Data Register (MDIOS_DOUTR6), Address offset: 198h */
__IO uint32_t DOUTR7; /*!< MDIOS Output Data Register (MDIOS_DOUTR7), Address offset: 19Ch */
__IO uint32_t DOUTR8; /*!< MDIOS Output Data Register (MDIOS_DOUTR8), Address offset: 1A0h */
__IO uint32_t DOUTR9; /*!< MDIOS Output Data Register (MDIOS_DOUTR9), Address offset: 1A4h */
__IO uint32_t DOUTR10; /*!< MDIOS Output Data Register (MDIOS_DOUTR10), Address offset: 1A8h */
__IO uint32_t DOUTR11; /*!< MDIOS Output Data Register (MDIOS_DOUTR11), Address offset: 1ACh */
__IO uint32_t DOUTR12; /*!< MDIOS Output Data Register (MDIOS_DOUTR12), Address offset: 1B0h */
__IO uint32_t DOUTR13; /*!< MDIOS Output Data Register (MDIOS_DOUTR13), Address offset: 1B4h */
__IO uint32_t DOUTR14; /*!< MDIOS Output Data Register (MDIOS_DOUTR14), Address offset: 1B8h */
__IO uint32_t DOUTR15; /*!< MDIOS Output Data Register (MDIOS_DOUTR15), Address offset: 1BCh */
__IO uint32_t DOUTR16; /*!< MDIOS Output Data Register (MDIOS_DOUTR16), Address offset: 1C0h */
__IO uint32_t DOUTR17; /*!< MDIOS Output Data Register (MDIOS_DOUTR17), Address offset: 1C4h */
__IO uint32_t DOUTR18; /*!< MDIOS Output Data Register (MDIOS_DOUTR18), Address offset: 1C8h */
__IO uint32_t DOUTR19; /*!< MDIOS Output Data Register (MDIOS_DOUTR19), Address offset: 1CCh */
__IO uint32_t DOUTR20; /*!< MDIOS Output Data Register (MDIOS_DOUTR20), Address offset: 1D0h */
__IO uint32_t DOUTR21; /*!< MDIOS Output Data Register (MDIOS_DOUTR21), Address offset: 1D4h */
__IO uint32_t DOUTR22; /*!< MDIOS Output Data Register (MDIOS_DOUTR22), Address offset: 1D8h */
__IO uint32_t DOUTR23; /*!< MDIOS Output Data Register (MDIOS_DOUTR23), Address offset: 1DCh */
__IO uint32_t DOUTR24; /*!< MDIOS Output Data Register (MDIOS_DOUTR24), Address offset: 1E0h */
__IO uint32_t DOUTR25; /*!< MDIOS Output Data Register (MDIOS_DOUTR25), Address offset: 1E4h */
__IO uint32_t DOUTR26; /*!< MDIOS Output Data Register (MDIOS_DOUTR26), Address offset: 1E8h */
__IO uint32_t DOUTR27; /*!< MDIOS Output Data Register (MDIOS_DOUTR27), Address offset: 1ECh */
__IO uint32_t DOUTR28; /*!< MDIOS Output Data Register (MDIOS_DOUTR28), Address offset: 1F0h */
__IO uint32_t DOUTR29; /*!< MDIOS Output Data Register (MDIOS_DOUTR29), Address offset: 1F4h */
__IO uint32_t DOUTR30; /*!< MDIOS Output Data Register (MDIOS_DOUTR30), Address offset: 1F8h */
__IO uint32_t DOUTR31; /*!< MDIOS Output Data Register (MDIOS_DOUTR31), Address offset: 1FCh */
} MDIOS_TypeDef;
/** @addtogroup Peripheral_memory_map
* @{
*/
#define RAMITCM_BASE 0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */
#define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM */
#define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */
#define RAMDTCM_BASE 0x20000000U /*!< Base address of : 128KB system data RAM accessible over DTCM */
#define PERIPH_BASE 0x40000000U /*!< Base address of : AHB/ABP Peripherals */
#define BKPSRAM_BASE 0x40024000U /*!< Base address of : Backup SRAM(4 KB) */
#define QSPI_BASE 0x90000000U /*!< Base address of : QSPI memories accessible over AXI */
#define FMC_R_BASE 0xA0000000U /*!< Base address of : FMC Control registers */
#define QSPI_R_BASE 0xA0001000U /*!< Base address of : QSPI Control registers */
#define SRAM1_BASE 0x20020000U /*!< Base address of : 368KB RAM1 accessible over AXI/AHB */
#define SRAM2_BASE 0x2007C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
#define FLASH_END 0x081FFFFFU /*!< FLASH end address */
/* Legacy define */
#define FLASH_BASE FLASHAXI_BASE
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
/*!< APB1 peripherals */
#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
#define CAN3_BASE (APB1PERIPH_BASE + 0x3400U)
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U)
#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
#define I2C4_BASE (APB1PERIPH_BASE + 0x6000U)
#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
#define CEC_BASE (APB1PERIPH_BASE + 0x6C00U)
#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
#define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
/*!< APB2 peripherals */
#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
#define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00U)
#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U)
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
#define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U)
#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
#define SAI2_Block_A_BASE (SAI2_BASE + 0x004U)
#define SAI2_Block_B_BASE (SAI2_BASE + 0x024U)
#define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
#define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
#define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
#define DFSDM1_BASE (APB2PERIPH_BASE + 0x7400U)
#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U)
#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U)
#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U)
#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U)
#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80U)
#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0U)
#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0U)
#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0U)
#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U)
#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)
#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200U)
#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280U)
#define MDIOS_BASE (APB2PERIPH_BASE + 0x7800U)
/*!< AHB1 peripherals */
#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
#define UID_BASE 0x1FF0F420U /*!< Unique device ID register base address */
#define FLASHSIZE_BASE 0x1FF0F442U /*!< FLASH Size register base address */
#define PACKAGESIZE_BASE 0x1FFF7BF0U /*!< Package size register base address */
#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
#define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
#define ETH_MAC_BASE (ETH_BASE)
#define ETH_MMC_BASE (ETH_BASE + 0x0100U)
#define ETH_PTP_BASE (ETH_BASE + 0x0700U)
#define ETH_DMA_BASE (ETH_BASE + 0x1000U)
#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
/*!< AHB2 peripherals */
#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
#define JPEG_BASE (AHB2PERIPH_BASE + 0x51000U)
#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
/*!< FMC Bankx registers base address */
#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
/* Debug MCU registers base address */
#define DBGMCU_BASE 0xE0042000U
/*!< USB registers base address */
#define USB_OTG_HS_PERIPH_BASE 0x40040000U
#define USB_OTG_FS_PERIPH_BASE 0x50000000U
#define USB_OTG_GLOBAL_BASE 0x000U
#define USB_OTG_DEVICE_BASE 0x800U
#define USB_OTG_IN_ENDPOINT_BASE 0x900U
#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
#define USB_OTG_EP_REG_SIZE 0x20U
#define USB_OTG_HOST_BASE 0x400U
#define USB_OTG_HOST_PORT_BASE 0x440U
#define USB_OTG_HOST_CHANNEL_BASE 0x500U
#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
#define USB_OTG_PCGCCTL_BASE 0xE00U
#define USB_OTG_FIFO_BASE 0x1000U
#define USB_OTG_FIFO_SIZE 0x1000U
/**
* @}
*/
/** @addtogroup Peripheral_declaration
* @{
*/
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
#define RTC ((RTC_TypeDef *) RTC_BASE)
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
#define USART2 ((USART_TypeDef *) USART2_BASE)
#define USART3 ((USART_TypeDef *) USART3_BASE)
#define UART4 ((USART_TypeDef *) UART4_BASE)
#define UART5 ((USART_TypeDef *) UART5_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
#define CEC ((CEC_TypeDef *) CEC_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
#define UART7 ((USART_TypeDef *) UART7_BASE)
#define UART8 ((USART_TypeDef *) UART8_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
#define USART6 ((USART_TypeDef *) USART6_BASE)
#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define RCC ((RCC_TypeDef *) RCC_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
#define ETH ((ETH_TypeDef *) ETH_BASE)
#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
#define RNG ((RNG_TypeDef *) RNG_BASE)
#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
#define CAN3 ((CAN_TypeDef *) CAN3_BASE)
#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
#define JPEG ((JPEG_TypeDef *) JPEG_BASE)
/**
* @}
*/
/** @addtogroup Exported_constants
* @{
*/
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
/******************************************************************************/
/* Peripheral Registers_Bits_Definition */
/******************************************************************************/
/******************************************************************************/
/* */
/* Analog to Digital Converter */
/* */
/******************************************************************************/
/******************** Bit definition for ADC_SR register ********************/
#define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
#define ADC_SR_EOC 0x00000002U /*!<End of conversion */
#define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
#define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
#define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
#define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
/******************* Bit definition for ADC_CR1 register ********************/
#define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
#define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
#define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
#define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
#define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
#define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
#define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
#define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
#define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
#define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
#define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
#define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
#define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
#define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
#define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
#define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
#define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
#define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
#define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
#define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
#define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
#define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
#define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
#define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
/******************* Bit definition for ADC_CR2 register ********************/
#define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
#define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
#define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
#define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
#define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
#define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
#define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
#define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
#define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
#define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
#define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
#define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
#define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
#define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
#define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
#define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
#define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
#define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
#define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
#define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
#define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
#define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
#define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
#define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
/****************** Bit definition for ADC_SMPR1 register *******************/
#define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
#define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
#define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
#define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
#define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
#define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
#define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
#define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
#define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
#define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
#define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
#define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
#define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
#define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
#define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
#define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
#define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
#define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
#define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
#define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
#define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
#define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
#define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
#define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
#define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
#define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
#define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
#define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
#define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
#define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
#define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
#define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
#define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
#define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
#define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
#define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
/****************** Bit definition for ADC_SMPR2 register *******************/
#define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
#define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
#define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
#define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
#define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
#define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
#define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
#define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
#define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
#define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
#define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
#define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
#define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
#define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
#define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
#define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
#define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
#define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
#define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
#define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
#define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
#define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
#define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
#define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
#define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
#define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
#define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
#define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
#define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
#define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
#define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
#define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
#define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
#define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
#define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
#define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
#define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
#define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
#define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
#define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
/****************** Bit definition for ADC_JOFR1 register *******************/
#define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
/****************** Bit definition for ADC_JOFR2 register *******************/
#define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
/****************** Bit definition for ADC_JOFR3 register *******************/
#define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
/****************** Bit definition for ADC_JOFR4 register *******************/
#define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
/******************* Bit definition for ADC_HTR register ********************/
#define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
/******************* Bit definition for ADC_LTR register ********************/
#define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
/******************* Bit definition for ADC_SQR1 register *******************/
#define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
#define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
#define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
#define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
#define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
#define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
#define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
#define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
#define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
#define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
#define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
#define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
#define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
#define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
#define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
#define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
#define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
#define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
#define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
#define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
#define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
#define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
#define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
#define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
#define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
#define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
#define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
#define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
#define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
/******************* Bit definition for ADC_SQR2 register *******************/
#define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
#define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
#define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
#define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
#define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
#define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
#define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
#define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
#define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
#define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
#define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
#define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
#define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
#define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
#define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
#define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
#define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
#define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
#define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
#define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
#define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
#define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
#define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
#define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
#define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
#define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
#define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
#define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
#define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
#define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
#define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
#define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
#define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
#define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
#define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
#define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
/******************* Bit definition for ADC_SQR3 register *******************/
#define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
#define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
#define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
#define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
#define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
#define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
#define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
#define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
#define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
#define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
#define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
#define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
#define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
#define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
#define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
#define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
#define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
#define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
#define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
#define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
#define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
#define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
#define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
#define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
#define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
#define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
#define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
#define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
#define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
#define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
#define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
#define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
#define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
#define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
#define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
#define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
/******************* Bit definition for ADC_JSQR register *******************/
#define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
#define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
#define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
#define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
#define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
#define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
#define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
#define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
#define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
#define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
#define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
#define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
#define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
#define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
#define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
#define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
#define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
#define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
#define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
#define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
#define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
#define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
#define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
#define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
#define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
#define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
#define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
/******************* Bit definition for ADC_JDR1 register *******************/
#define ADC_JDR1_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
/******************* Bit definition for ADC_JDR2 register *******************/
#define ADC_JDR2_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
/******************* Bit definition for ADC_JDR3 register *******************/
#define ADC_JDR3_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
/******************* Bit definition for ADC_JDR4 register *******************/
#define ADC_JDR4_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
/******************** Bit definition for ADC_DR register ********************/
#define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
#define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
/******************* Bit definition for ADC_CSR register ********************/
#define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
#define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
#define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
#define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
#define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
#define ADC_CSR_OVR1 0x00000020U /*!<ADC1 Overrun flag */
#define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
#define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
#define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
#define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
#define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
#define ADC_CSR_OVR2 0x00002000U /*!<ADC2 Overrun flag */
#define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
#define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
#define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
#define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
#define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
#define ADC_CSR_OVR3 0x00200000U /*!<ADC3 Overrun flag */
/* Legacy defines */
#define ADC_CSR_DOVR1 ADC_CSR_OVR1
#define ADC_CSR_DOVR2 ADC_CSR_OVR2
#define ADC_CSR_DOVR3 ADC_CSR_OVR3
/******************* Bit definition for ADC_CCR register ********************/
#define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
#define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
#define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
#define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
#define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
#define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
#define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
#define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
#define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
#define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
#define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
#define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
#define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
#define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
#define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
#define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
#define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
#define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
#define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
#define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
/******************* Bit definition for ADC_CDR register ********************/
#define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
#define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
/******************************************************************************/
/* */
/* Controller Area Network */
/* */
/******************************************************************************/
/*!<CAN control and status registers */
/******************* Bit definition for CAN_MCR register ********************/
#define CAN_MCR_INRQ 0x00000001U /*!<Initialization Request */
#define CAN_MCR_SLEEP 0x00000002U /*!<Sleep Mode Request */
#define CAN_MCR_TXFP 0x00000004U /*!<Transmit FIFO Priority */
#define CAN_MCR_RFLM 0x00000008U /*!<Receive FIFO Locked Mode */
#define CAN_MCR_NART 0x00000010U /*!<No Automatic Retransmission */
#define CAN_MCR_AWUM 0x00000020U /*!<Automatic Wakeup Mode */
#define CAN_MCR_ABOM 0x00000040U /*!<Automatic Bus-Off Management */
#define CAN_MCR_TTCM 0x00000080U /*!<Time Triggered Communication Mode */
#define CAN_MCR_RESET 0x00008000U /*!<bxCAN software master reset */
/******************* Bit definition for CAN_MSR register ********************/
#define CAN_MSR_INAK 0x00000001U /*!<Initialization Acknowledge */
#define CAN_MSR_SLAK 0x00000002U /*!<Sleep Acknowledge */
#define CAN_MSR_ERRI 0x00000004U /*!<Error Interrupt */
#define CAN_MSR_WKUI 0x00000008U /*!<Wakeup Interrupt */
#define CAN_MSR_SLAKI 0x00000010U /*!<Sleep Acknowledge Interrupt */
#define CAN_MSR_TXM 0x00000100U /*!<Transmit Mode */
#define CAN_MSR_RXM 0x00000200U /*!<Receive Mode */
#define CAN_MSR_SAMP 0x00000400U /*!<Last Sample Point */
#define CAN_MSR_RX 0x00000800U /*!<CAN Rx Signal */
/******************* Bit definition for CAN_TSR register ********************/
#define CAN_TSR_RQCP0 0x00000001U /*!<Request Completed Mailbox0 */
#define CAN_TSR_TXOK0 0x00000002U /*!<Transmission OK of Mailbox0 */
#define CAN_TSR_ALST0 0x00000004U /*!<Arbitration Lost for Mailbox0 */
#define CAN_TSR_TERR0 0x00000008U /*!<Transmission Error of Mailbox0 */
#define CAN_TSR_ABRQ0 0x00000080U /*!<Abort Request for Mailbox0 */
#define CAN_TSR_RQCP1 0x00000100U /*!<Request Completed Mailbox1 */
#define CAN_TSR_TXOK1 0x00000200U /*!<Transmission OK of Mailbox1 */
#define CAN_TSR_ALST1 0x00000400U /*!<Arbitration Lost for Mailbox1 */
#define CAN_TSR_TERR1 0x00000800U /*!<Transmission Error of Mailbox1 */
#define CAN_TSR_ABRQ1 0x00008000U /*!<Abort Request for Mailbox 1 */
#define CAN_TSR_RQCP2 0x00010000U /*!<Request Completed Mailbox2 */
#define CAN_TSR_TXOK2 0x00020000U /*!<Transmission OK of Mailbox 2 */
#define CAN_TSR_ALST2 0x00040000U /*!<Arbitration Lost for mailbox 2 */
#define CAN_TSR_TERR2 0x00080000U /*!<Transmission Error of Mailbox 2 */
#define CAN_TSR_ABRQ2 0x00800000U /*!<Abort Request for Mailbox 2 */
#define CAN_TSR_CODE 0x03000000U /*!<Mailbox Code */
#define CAN_TSR_TME 0x1C000000U /*!<TME[2:0] bits */
#define CAN_TSR_TME0 0x04000000U /*!<Transmit Mailbox 0 Empty */
#define CAN_TSR_TME1 0x08000000U /*!<Transmit Mailbox 1 Empty */
#define CAN_TSR_TME2 0x10000000U /*!<Transmit Mailbox 2 Empty */
#define CAN_TSR_LOW 0xE0000000U /*!<LOW[2:0] bits */
#define CAN_TSR_LOW0 0x20000000U /*!<Lowest Priority Flag for Mailbox 0 */
#define CAN_TSR_LOW1 0x40000000U /*!<Lowest Priority Flag for Mailbox 1 */
#define CAN_TSR_LOW2 0x80000000U /*!<Lowest Priority Flag for Mailbox 2 */
/******************* Bit definition for CAN_RF0R register *******************/
#define CAN_RF0R_FMP0 0x00000003U /*!<FIFO 0 Message Pending */
#define CAN_RF0R_FULL0 0x00000008U /*!<FIFO 0 Full */
#define CAN_RF0R_FOVR0 0x00000010U /*!<FIFO 0 Overrun */
#define CAN_RF0R_RFOM0 0x00000020U /*!<Release FIFO 0 Output Mailbox */
/******************* Bit definition for CAN_RF1R register *******************/
#define CAN_RF1R_FMP1 0x00000003U /*!<FIFO 1 Message Pending */
#define CAN_RF1R_FULL1 0x00000008U /*!<FIFO 1 Full */
#define CAN_RF1R_FOVR1 0x00000010U /*!<FIFO 1 Overrun */
#define CAN_RF1R_RFOM1 0x00000020U /*!<Release FIFO 1 Output Mailbox */
/******************** Bit definition for CAN_IER register *******************/
#define CAN_IER_TMEIE 0x00000001U /*!<Transmit Mailbox Empty Interrupt Enable */
#define CAN_IER_FMPIE0 0x00000002U /*!<FIFO Message Pending Interrupt Enable */
#define CAN_IER_FFIE0 0x00000004U /*!<FIFO Full Interrupt Enable */
#define CAN_IER_FOVIE0 0x00000008U /*!<FIFO Overrun Interrupt Enable */
#define CAN_IER_FMPIE1 0x00000010U /*!<FIFO Message Pending Interrupt Enable */
#define CAN_IER_FFIE1 0x00000020U /*!<FIFO Full Interrupt Enable */
#define CAN_IER_FOVIE1 0x00000040U /*!<FIFO Overrun Interrupt Enable */
#define CAN_IER_EWGIE 0x00000100U /*!<Error Warning Interrupt Enable */
#define CAN_IER_EPVIE 0x00000200U /*!<Error Passive Interrupt Enable */
#define CAN_IER_BOFIE 0x00000400U /*!<Bus-Off Interrupt Enable */
#define CAN_IER_LECIE 0x00000800U /*!<Last Error Code Interrupt Enable */
#define CAN_IER_ERRIE 0x00008000U /*!<Error Interrupt Enable */
#define CAN_IER_WKUIE 0x00010000U /*!<Wakeup Interrupt Enable */
#define CAN_IER_SLKIE 0x00020000U /*!<Sleep Interrupt Enable */
/******************** Bit definition for CAN_ESR register *******************/
#define CAN_ESR_EWGF 0x00000001U /*!<Error Warning Flag */
#define CAN_ESR_EPVF 0x00000002U /*!<Error Passive Flag */
#define CAN_ESR_BOFF 0x00000004U /*!<Bus-Off Flag */
#define CAN_ESR_LEC 0x00000070U /*!<LEC[2:0] bits (Last Error Code) */
#define CAN_ESR_LEC_0 0x00000010U /*!<Bit 0 */
#define CAN_ESR_LEC_1 0x00000020U /*!<Bit 1 */
#define CAN_ESR_LEC_2 0x00000040U /*!<Bit 2 */
#define CAN_ESR_TEC 0x00FF0000U /*!<Least significant byte of the 9-bit Transmit Error Counter */
#define CAN_ESR_REC 0xFF000000U /*!<Receive Error Counter */
/******************* Bit definition for CAN_BTR register ********************/
#define CAN_BTR_BRP 0x000003FFU /*!<Baud Rate Prescaler */
#define CAN_BTR_TS1 0x000F0000U /*!<Time Segment 1 */
#define CAN_BTR_TS1_0 0x00010000U /*!<Bit 0 */
#define CAN_BTR_TS1_1 0x00020000U /*!<Bit 1 */
#define CAN_BTR_TS1_2 0x00040000U /*!<Bit 2 */
#define CAN_BTR_TS1_3 0x00080000U /*!<Bit 3 */
#define CAN_BTR_TS2 0x00700000U /*!<Time Segment 2 */
#define CAN_BTR_TS2_0 0x00100000U /*!<Bit 0 */
#define CAN_BTR_TS2_1 0x00200000U /*!<Bit 1 */
#define CAN_BTR_TS2_2 0x00400000U /*!<Bit 2 */
#define CAN_BTR_SJW 0x03000000U /*!<Resynchronization Jump Width */
#define CAN_BTR_SJW_0 0x01000000U /*!<Bit 0 */
#define CAN_BTR_SJW_1 0x02000000U /*!<Bit 1 */
#define CAN_BTR_LBKM 0x40000000U /*!<Loop Back Mode (Debug) */
#define CAN_BTR_SILM 0x80000000U /*!<Silent Mode */
/*!<Mailbox registers */
/****************** Bit definition for CAN_TI0R register ********************/
#define CAN_TI0R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
#define CAN_TI0R_RTR 0x00000002U /*!<Remote Transmission Request */
#define CAN_TI0R_IDE 0x00000004U /*!<Identifier Extension */
#define CAN_TI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
#define CAN_TI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
/****************** Bit definition for CAN_TDT0R register *******************/
#define CAN_TDT0R_DLC 0x0000000FU /*!<Data Length Code */
#define CAN_TDT0R_TGT 0x00000100U /*!<Transmit Global Time */
#define CAN_TDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
/****************** Bit definition for CAN_TDL0R register *******************/
#define CAN_TDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
#define CAN_TDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
#define CAN_TDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
#define CAN_TDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
/****************** Bit definition for CAN_TDH0R register *******************/
#define CAN_TDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
#define CAN_TDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
#define CAN_TDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
#define CAN_TDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
/******************* Bit definition for CAN_TI1R register *******************/
#define CAN_TI1R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
#define CAN_TI1R_RTR 0x00000002U /*!<Remote Transmission Request */
#define CAN_TI1R_IDE 0x00000004U /*!<Identifier Extension */
#define CAN_TI1R_EXID 0x001FFFF8U /*!<Extended Identifier */
#define CAN_TI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
/******************* Bit definition for CAN_TDT1R register ******************/
#define CAN_TDT1R_DLC 0x0000000FU /*!<Data Length Code */
#define CAN_TDT1R_TGT 0x00000100U /*!<Transmit Global Time */
#define CAN_TDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
/******************* Bit definition for CAN_TDL1R register ******************/
#define CAN_TDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
#define CAN_TDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
#define CAN_TDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
#define CAN_TDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
/******************* Bit definition for CAN_TDH1R register ******************/
#define CAN_TDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
#define CAN_TDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
#define CAN_TDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
#define CAN_TDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
/******************* Bit definition for CAN_TI2R register *******************/
#define CAN_TI2R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
#define CAN_TI2R_RTR 0x00000002U /*!<Remote Transmission Request */
#define CAN_TI2R_IDE 0x00000004U /*!<Identifier Extension */
#define CAN_TI2R_EXID 0x001FFFF8U /*!<Extended identifier */
#define CAN_TI2R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
/******************* Bit definition for CAN_TDT2R register ******************/
#define CAN_TDT2R_DLC 0x0000000FU /*!<Data Length Code */
#define CAN_TDT2R_TGT 0x00000100U /*!<Transmit Global Time */
#define CAN_TDT2R_TIME 0xFFFF0000U /*!<Message Time Stamp */
/******************* Bit definition for CAN_TDL2R register ******************/
#define CAN_TDL2R_DATA0 0x000000FFU /*!<Data byte 0 */
#define CAN_TDL2R_DATA1 0x0000FF00U /*!<Data byte 1 */
#define CAN_TDL2R_DATA2 0x00FF0000U /*!<Data byte 2 */
#define CAN_TDL2R_DATA3 0xFF000000U /*!<Data byte 3 */
/******************* Bit definition for CAN_TDH2R register ******************/
#define CAN_TDH2R_DATA4 0x000000FFU /*!<Data byte 4 */
#define CAN_TDH2R_DATA5 0x0000FF00U /*!<Data byte 5 */
#define CAN_TDH2R_DATA6 0x00FF0000U /*!<Data byte 6 */
#define CAN_TDH2R_DATA7 0xFF000000U /*!<Data byte 7 */
/******************* Bit definition for CAN_RI0R register *******************/
#define CAN_RI0R_RTR 0x00000002U /*!<Remote Transmission Request */
#define CAN_RI0R_IDE 0x00000004U /*!<Identifier Extension */
#define CAN_RI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
#define CAN_RI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
/******************* Bit definition for CAN_RDT0R register ******************/
#define CAN_RDT0R_DLC 0x0000000FU /*!<Data Length Code */
#define CAN_RDT0R_FMI 0x0000FF00U /*!<Filter Match Index */
#define CAN_RDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
/******************* Bit definition for CAN_RDL0R register ******************/
#define CAN_RDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
#define CAN_RDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
#define CAN_RDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
#define CAN_RDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
/******************* Bit definition for CAN_RDH0R register ******************/
#define CAN_RDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
#define CAN_RDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
#define CAN_RDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
#define CAN_RDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
/******************* Bit definition for CAN_RI1R register *******************/
#define CAN_RI1R_RTR 0x00000002U /*!<Remote Transmission Request */
#define CAN_RI1R_IDE 0x00000004U /*!<Identifier Extension */
#define CAN_RI1R_EXID 0x001FFFF8U /*!<Extended identifier */
#define CAN_RI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
/******************* Bit definition for CAN_RDT1R register ******************/
#define CAN_RDT1R_DLC 0x0000000FU /*!<Data Length Code */
#define CAN_RDT1R_FMI 0x0000FF00U /*!<Filter Match Index */
#define CAN_RDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
/******************* Bit definition for CAN_RDL1R register ******************/
#define CAN_RDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
#define CAN_RDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
#define CAN_RDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
#define CAN_RDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
/******************* Bit definition for CAN_RDH1R register ******************/
#define CAN_RDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
#define CAN_RDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
#define CAN_RDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
#define CAN_RDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
/*!<CAN filter registers */
/******************* Bit definition for CAN_FMR register ********************/
#define CAN_FMR_FINIT ((uint8_t)0x01U) /*!<Filter Init Mode */
#define CAN_FMR_CAN2SB 0x00003F00U /*!<CAN2 start bank */
/******************* Bit definition for CAN_FM1R register *******************/
#define CAN_FM1R_FBM 0x3FFFU /*!<Filter Mode */
#define CAN_FM1R_FBM0 0x0001U /*!<Filter Init Mode bit 0 */
#define CAN_FM1R_FBM1 0x0002U /*!<Filter Init Mode bit 1 */
#define CAN_FM1R_FBM2 0x0004U /*!<Filter Init Mode bit 2 */
#define CAN_FM1R_FBM3 0x0008U /*!<Filter Init Mode bit 3 */
#define CAN_FM1R_FBM4 0x0010U /*!<Filter Init Mode bit 4 */
#define CAN_FM1R_FBM5 0x0020U /*!<Filter Init Mode bit 5 */
#define CAN_FM1R_FBM6 0x0040U /*!<Filter Init Mode bit 6 */
#define CAN_FM1R_FBM7 0x0080U /*!<Filter Init Mode bit 7 */
#define CAN_FM1R_FBM8 0x0100U /*!<Filter Init Mode bit 8 */
#define CAN_FM1R_FBM9 0x0200U /*!<Filter Init Mode bit 9 */
#define CAN_FM1R_FBM10 0x0400U /*!<Filter Init Mode bit 10 */
#define CAN_FM1R_FBM11 0x0800U /*!<Filter Init Mode bit 11 */
#define CAN_FM1R_FBM12 0x1000U /*!<Filter Init Mode bit 12 */
#define CAN_FM1R_FBM13 0x2000U /*!<Filter Init Mode bit 13 */
/******************* Bit definition for CAN_FS1R register *******************/
#define CAN_FS1R_FSC 0x00003FFFU /*!<Filter Scale Configuration */
#define CAN_FS1R_FSC0 0x00000001U /*!<Filter Scale Configuration bit 0 */
#define CAN_FS1R_FSC1 0x00000002U /*!<Filter Scale Configuration bit 1 */
#define CAN_FS1R_FSC2 0x00000004U /*!<Filter Scale Configuration bit 2 */
#define CAN_FS1R_FSC3 0x00000008U /*!<Filter Scale Configuration bit 3 */
#define CAN_FS1R_FSC4 0x00000010U /*!<Filter Scale Configuration bit 4 */
#define CAN_FS1R_FSC5 0x00000020U /*!<Filter Scale Configuration bit 5 */
#define CAN_FS1R_FSC6 0x00000040U /*!<Filter Scale Configuration bit 6 */
#define CAN_FS1R_FSC7 0x00000080U /*!<Filter Scale Configuration bit 7 */
#define CAN_FS1R_FSC8 0x00000100U /*!<Filter Scale Configuration bit 8 */
#define CAN_FS1R_FSC9 0x00000200U /*!<Filter Scale Configuration bit 9 */
#define CAN_FS1R_FSC10 0x00000400U /*!<Filter Scale Configuration bit 10 */
#define CAN_FS1R_FSC11 0x00000800U /*!<Filter Scale Configuration bit 11 */
#define CAN_FS1R_FSC12 0x00001000U /*!<Filter Scale Configuration bit 12 */
#define CAN_FS1R_FSC13 0x00002000U /*!<Filter Scale Configuration bit 13 */
/****************** Bit definition for CAN_FFA1R register *******************/
#define CAN_FFA1R_FFA 0x00003FFFU /*!<Filter FIFO Assignment */
#define CAN_FFA1R_FFA0 0x00000001U /*!<Filter FIFO Assignment for Filter 0 */
#define CAN_FFA1R_FFA1 0x00000002U /*!<Filter FIFO Assignment for Filter 1 */
#define CAN_FFA1R_FFA2 0x00000004U /*!<Filter FIFO Assignment for Filter 2 */
#define CAN_FFA1R_FFA3 0x00000008U /*!<Filter FIFO Assignment for Filter 3 */
#define CAN_FFA1R_FFA4 0x00000010U /*!<Filter FIFO Assignment for Filter 4 */
#define CAN_FFA1R_FFA5 0x00000020U /*!<Filter FIFO Assignment for Filter 5 */
#define CAN_FFA1R_FFA6 0x00000040U /*!<Filter FIFO Assignment for Filter 6 */
#define CAN_FFA1R_FFA7 0x00000080U /*!<Filter FIFO Assignment for Filter 7 */
#define CAN_FFA1R_FFA8 0x00000100U /*!<Filter FIFO Assignment for Filter 8 */
#define CAN_FFA1R_FFA9 0x00000200U /*!<Filter FIFO Assignment for Filter 9 */
#define CAN_FFA1R_FFA10 0x00000400U /*!<Filter FIFO Assignment for Filter 10 */
#define CAN_FFA1R_FFA11 0x00000800U /*!<Filter FIFO Assignment for Filter 11 */
#define CAN_FFA1R_FFA12 0x00001000U /*!<Filter FIFO Assignment for Filter 12 */
#define CAN_FFA1R_FFA13 0x00002000U /*!<Filter FIFO Assignment for Filter 13 */
/******************* Bit definition for CAN_FA1R register *******************/
#define CAN_FA1R_FACT 0x00003FFFU /*!<Filter Active */
#define CAN_FA1R_FACT0 0x00000001U /*!<Filter 0 Active */
#define CAN_FA1R_FACT1 0x00000002U /*!<Filter 1 Active */
#define CAN_FA1R_FACT2 0x00000004U /*!<Filter 2 Active */
#define CAN_FA1R_FACT3 0x00000008U /*!<Filter 3 Active */
#define CAN_FA1R_FACT4 0x00000010U /*!<Filter 4 Active */
#define CAN_FA1R_FACT5 0x00000020U /*!<Filter 5 Active */
#define CAN_FA1R_FACT6 0x00000040U /*!<Filter 6 Active */
#define CAN_FA1R_FACT7 0x00000080U /*!<Filter 7 Active */
#define CAN_FA1R_FACT8 0x00000100U /*!<Filter 8 Active */
#define CAN_FA1R_FACT9 0x00000200U /*!<Filter 9 Active */
#define CAN_FA1R_FACT10 0x00000400U /*!<Filter 10 Active */
#define CAN_FA1R_FACT11 0x00000800U /*!<Filter 11 Active */
#define CAN_FA1R_FACT12 0x00001000U /*!<Filter 12 Active */
#define CAN_FA1R_FACT13 0x00002000U /*!<Filter 13 Active */
/******************* Bit definition for CAN_F0R1 register *******************/
#define CAN_F0R1_FB0 0x00000001U /*!<Filter bit 0 */
#define CAN_F0R1_FB1 0x00000002U /*!<Filter bit 1 */
#define CAN_F0R1_FB2 0x00000004U /*!<Filter bit 2 */
#define CAN_F0R1_FB3 0x00000008U /*!<Filter bit 3 */
#define CAN_F0R1_FB4 0x00000010U /*!<Filter bit 4 */
#define CAN_F0R1_FB5 0x00000020U /*!<Filter bit 5 */
#define CAN_F0R1_FB6 0x00000040U /*!<Filter bit 6 */
#define CAN_F0R1_FB7 0x00000080U /*!<Filter bit 7 */
#define CAN_F0R1_FB8 0x00000100U /*!<Filter bit 8 */
#define CAN_F0R1_FB9 0x00000200U /*!<Filter bit 9 */
#define CAN_F0R1_FB10 0x00000400U /*!<Filter bit 10 */
#define CAN_F0R1_FB11 0x00000800U /*!<Filter bit 11 */
#define CAN_F0R1_FB12 0x00001000U /*!<Filter bit 12 */
#define CAN_F0R1_FB13 0x00002000U /*!<Filter bit 13 */
#define CAN_F0R1_FB14 0x00004000U /*!<Filter bit 14 */
#define CAN_F0R1_FB15 0x00008000U /*!<Filter bit 15 */
#define CAN_F0R1_FB16 0x00010000U /*!<Filter bit 16 */
#define CAN_F0R1_FB17 0x00020000U /*!<Filter bit 17 */
#define CAN_F0R1_FB18 0x00040000U /*!<Filter bit 18 */
#define CAN_F0R1_FB19 0x00080000U /*!<Filter bit 19 */
#define CAN_F0R1_FB20 0x00100000U /*!<Filter bit 20 */
#define CAN_F0R1_FB21 0x00200000U /*!<Filter bit 21 */
#define CAN_F0R1_FB22 0x00400000U /*!<Filter bit 22 */
#define CAN_F0R1_FB23 0x00800000U /*!<Filter bit 23 */
#define CAN_F0R1_FB24 0x01000000U /*!<Filter bit 24 */
#define CAN_F0R1_FB25 0x02000000U /*!<Filter bit 25 */
#define CAN_F0R1_FB26 0x04000000U /*!<Filter bit 26 */
#define CAN_F0R1_FB27 0x08000000U /*!<Filter bit 27 */
#define CAN_F0R1_FB28 0x10000000U /*!<Filter bit 28 */
#define CAN_F0R1_FB29 0x20000000U /*!<Filter bit 29 */
#define CAN_F0R1_FB30 0x40000000U /*!<Filter bit 30 */
#define CAN_F0R1_FB31 0x80000000U /*!<Filter bit 31 */
/******************* Bit definition for CAN_F1R1 register *******************/
#define CAN_F1R1_FB0 0x00000001U /*!<Filter bit 0 */
#define CAN_F1R1_FB1 0x00000002U /*!<Filter bit 1 */
#define CAN_F1R1_FB2 0x00000004U /*!<Filter bit 2 */
#define CAN_F1R1_FB3 0x00000008U /*!<Filter bit 3 */
#define CAN_F1R1_FB4 0x00000010U /*!<Filter bit 4 */
#define CAN_F1R1_FB5 0x00000020U /*!<Filter bit 5 */
#define CAN_F1R1_FB6 0x00000040U /*!<Filter bit 6 */
#define CAN_F1R1_FB7 0x00000080U /*!<Filter bit 7 */
#define CAN_F1R1_FB8 0x00000100U /*!<Filter bit 8 */
#define CAN_F1R1_FB9 0x00000200U /*!<Filter bit 9 */
#define CAN_F1R1_FB10 0x00000400U /*!<Filter bit 10 */
#define CAN_F1R1_FB11 0x00000800U /*!<Filter bit 11 */
#define CAN_F1R1_FB12 0x00001000U /*!<Filter bit 12 */
#define CAN_F1R1_FB13 0x00002000U /*!<Filter bit 13 */
#define CAN_F1R1_FB14 0x00004000U /*!<Filter bit 14 */
#define CAN_F1R1_FB15 0x00008000U /*!<Filter bit 15 */
#define CAN_F1R1_FB16 0x00010000U /*!<Filter bit 16 */
#define CAN_F1R1_FB17 0x00020000U /*!<Filter bit 17 */
#define CAN_F1R1_FB18 0x00040000U /*!<Filter bit 18 */
#define CAN_F1R1_FB19 0x00080000U /*!<Filter bit 19 */
#define CAN_F1R1_FB20 0x00100000U /*!<Filter bit 20 */
#define CAN_F1R1_FB21 0x00200000U /*!<Filter bit 21 */
#define CAN_F1R1_FB22 0x00400000U /*!<Filter bit 22 */
#define CAN_F1R1_FB23 0x00800000U /*!<Filter bit 23 */
#define CAN_F1R1_FB24 0x01000000U /*!<Filter bit 24 */
#define CAN_F1R1_FB25 0x02000000U /*!<Filter bit 25 */
#define CAN_F1R1_FB26 0x04000000U /*!<Filter bit 26 */
#define CAN_F1R1_FB27 0x08000000U /*!<Filter bit 27 */
#define CAN_F1R1_FB28 0x10000000U /*!<Filter bit 28 */
#define CAN_F1R1_FB29 0x20000000U /*!<Filter bit 29 */
#define CAN_F1R1_FB30 0x40000000U /*!<Filter bit 30 */
#define CAN_F1R1_FB31 0x80000000U /*!<Filter bit 31 */
/******************* Bit definition for CAN_F2R1 register *******************/
#define CAN_F2R1_FB0 0x00000001U /*!<Filter bit 0 */
#define CAN_F2R1_FB1 0x00000002U /*!<Filter bit 1 */
#define CAN_F2R1_FB2 0x00000004U /*!<Filter bit 2 */
#define CAN_F2R1_FB3 0x00000008U /*!<Filter bit 3 */
#define CAN_F2R1_FB4 0x00000010U /*!<Filter bit 4 */
#define CAN_F2R1_FB5 0x00000020U /*!<Filter bit 5 */
#define CAN_F2R1_FB6 0x00000040U /*!<Filter bit 6 */
#define CAN_F2R1_FB7 0x00000080U /*!<Filter bit 7 */
#define CAN_F2R1_FB8 0x00000100U /*!<Filter bit 8 */
#define CAN_F2R1_FB9 0x00000200U /*!<Filter bit 9 */
#define CAN_F2R1_FB10 0x00000400U /*!<Filter bit 10 */
#define CAN_F2R1_FB11 0x00000800U /*!<Filter bit 11 */
#define CAN_F2R1_FB12 0x00001000U /*!<Filter bit 12 */
#define CAN_F2R1_FB13 0x00002000U /*!<Filter bit 13 */
#define CAN_F2R1_FB14 0x00004000U /*!<Filter bit 14 */
#define CAN_F2R1_FB15 0x00008000U /*!<Filter bit 15 */
#define CAN_F2R1_FB16 0x00010000U /*!<Filter bit 16 */
#define CAN_F2R1_FB17 0x00020000U /*!<Filter bit 17 */
#define CAN_F2R1_FB18 0x00040000U /*!<Filter bit 18 */
#define CAN_F2R1_FB19 0x00080000U /*!<Filter bit 19 */
#define CAN_F2R1_FB20 0x00100000U /*!<Filter bit 20 */
#define CAN_F2R1_FB21 0x00200000U /*!<Filter bit 21 */
#define CAN_F2R1_FB22 0x00400000U /*!<Filter bit 22 */
#define CAN_F2R1_FB23 0x00800000U /*!<Filter bit 23 */
#define CAN_F2R1_FB24 0x01000000U /*!<Filter bit 24 */
#define CAN_F2R1_FB25 0x02000000U /*!<Filter bit 25 */
#define CAN_F2R1_FB26 0x04000000U /*!<Filter bit 26 */
#define CAN_F2R1_FB27 0x08000000U /*!<Filter bit 27 */
#define CAN_F2R1_FB28 0x10000000U /*!<Filter bit 28 */
#define CAN_F2R1_FB29 0x20000000U /*!<Filter bit 29 */
#define CAN_F2R1_FB30 0x40000000U /*!<Filter bit 30 */
#define CAN_F2R1_FB31 0x80000000U /*!<Filter bit 31 */
/******************* Bit definition for CAN_F3R1 register *******************/
#define CAN_F3R1_FB0 0x00000001U /*!<Filter bit 0 */
#define CAN_F3R1_FB1 0x00000002U /*!<Filter bit 1 */
#define CAN_F3R1_FB2 0x00000004U /*!<Filter bit 2 */
#define CAN_F3R1_FB3 0x00000008U /*!<Filter bit 3 */
#define CAN_F3R1_FB4 0x00000010U /*!<Filter bit 4 */
#define CAN_F3R1_FB5 0x00000020U /*!<Filter bit 5 */
#define CAN_F3R1_FB6 0x00000040U /*!<Filter bit 6 */
#define CAN_F3R1_FB7 0x00000080U /*!<Filter bit 7 */
#define CAN_F3R1_FB8 0x00000100U /*!<Filter bit 8 */
#define CAN_F3R1_FB9 0x00000200U /*!<Filter bit 9 */
#define CAN_F3R1_FB10 0x00000400U /*!<Filter bit 10 */
#define CAN_F3R1_FB11 0x00000800U /*!<Filter bit 11 */
#define CAN_F3R1_FB12 0x00001000U /*!<Filter bit 12 */
#define CAN_F3R1_FB13 0x00002000U /*!<Filter bit 13 */
#define CAN_F3R1_FB14 0x00004000U /*!<Filter bit 14 */
#define CAN_F3R1_FB15 0x00008000U /*!<Filter bit 15 */
#define CAN_F3R1_FB16 0x00010000U /*!<Filter bit 16 */
#define CAN_F3R1_FB17 0x00020000U /*!<Filter bit 17 */
#define CAN_F3R1_FB18 0x00040000U /*!<Filter bit 18 */
#define CAN_F3R1_FB19 0x00080000U /*!<Filter bit 19 */
#define CAN_F3R1_FB20 0x00100000U /*!<Filter bit 20 */
#define CAN_F3R1_FB21 0x00200000U /*!<Filter bit 21 */
#define CAN_F3R1_FB22 0x00400000U /*!<Filter bit 22 */
#define CAN_F3R1_FB23 0x00800000U /*!<Filter bit 23 */
#define CAN_F3R1_FB24 0x01000000U /*!<Filter bit 24 */
#define CAN_F3R1_FB25 0x02000000U /*!<Filter bit 25 */
#define CAN_F3R1_FB26 0x04000000U /*!<Filter bit 26 */
#define CAN_F3R1_FB27 0x08000000U /*!<Filter bit 27 */
#define CAN_F3R1_FB28 0x10000000U /*!<Filter bit 28 */
#define CAN_F3R1_FB29 0x20000000U /*!<Filter bit 29 */
#define CAN_F3R1_FB30 0x40000000U /*!<Filter bit 30 */
#define CAN_F3R1_FB31 0x80000000U /*!<Filter bit 31 */
/******************* Bit definition for CAN_F4R1 register *******************/
#define CAN_F4R1_FB0 0x00000001U /*!<Filter bit 0 */
#define CAN_F4R1_FB1 0x00000002U /*!<Filter bit 1 */
#define CAN_F4R1_FB2 0x00000004U /*!<Filter bit 2 */
#define CAN_F4R1_FB3 0x00000008U /*!<Filter bit 3 */
#define CAN_F4R1_FB4 0x00000010U /*!<Filter bit 4 */
#define CAN_F4R1_FB5 0x00000020U /*!<Filter bit 5 */
#define CAN_F4R1_FB6 0x00000040U /*!<Filter bit 6 */
#define CAN_F4R1_FB7 0x00000080U /*!<Filter bit 7 */
#define CAN_F4R1_FB8 0x00000100U /*!<Filter bit 8 */
#define CAN_F4R1_FB9 0x00000200U /*!<Filter bit 9 */
#define CAN_F4R1_FB10 0x00000400U /*!<Filter bit 10 */
#define CAN_F4R1_FB11 0x00000800U /*!<Filter bit 11 */
#define CAN_F4R1_FB12 0x00001000U /*!<Filter bit 12 */
#define CAN_F4R1_FB13 0x00002000U /*!<Filter bit 13 */
#define CAN_F4R1_FB14 0x00004000U /*!<Filter bit 14 */
#define CAN_F4R1_FB15 0x00008000U /*!<Filter bit 15 */
#define CAN_F4R1_FB16 0x00010000U /*!<Filter bit 16 */
#define CAN_F4R1_FB17 0x00020000U /*!<Filter bit 17 */
#define CAN_F4R1_FB18 0x00040000U /*!<Filter bit 18 */
#define CAN_F4R1_FB19 0x00080000U /*!<Filter bit 19 */
#define CAN_F4R1_FB20 0x00100000U /*!<Filter bit 20 */
#define CAN_F4R1_FB21 0x00200000U /*!<Filter bit 21 */
#define CAN_F4R1_FB22 0x00400000U /*!<Filter bit 22 */
#define CAN_F4R1_FB23 0x00800000U /*!<Filter bit 23 */
#define CAN_F4R1_FB24 0x01000000U /*!<Filter bit 24 */
#define CAN_F4R1_FB25 0x02000000U /*!<Filter bit 25 */
#define CAN_F4R1_FB26 0x04000000U /*!<Filter bit 26 */
#define CAN_F4R1_FB27 0x08000000U /*!<Filter bit 27 */
#define CAN_F4R1_FB28 0x10000000U /*!<Filter bit 28 */
#define CAN_F4R1_FB29 0x20000000U /*!<Filter bit 29 */
#define CAN_F4R1_FB30 0x40000000U /*!<Filter bit 30 */
#define CAN_F4R1_FB31 0x80000000U /*!<Filter bit 31 */
/******************* Bit definition for CAN_F5R1 register *******************/
#define CAN_F5R1_FB0 0x00000001U /*!<Filter bit 0 */
#define CAN_F5R1_FB1 0x00000002U /*!<Filter bit 1 */
#define CAN_F5R1_FB2 0x00000004U /*!<Filter bit 2 */
#define CAN_F5R1_FB3 0x00000008U /*!<Filter bit 3 */
#define CAN_F5R1_FB4 0x00000010U /*!<Filter bit 4 */
#define CAN_F5R1_FB5 0x00000020U /*!<Filter bit 5 */
#define CAN_F5R1_FB6 0x00000040U /*!<Filter bit 6 */
#define CAN_F5R1_FB7 0x00000080U /*!<Filter bit 7 */
#define CAN_F5R1_FB8 0x00000100U /*!<Filter bit 8 */
#define CAN_F5R1_FB9 0x00000200U /*!<Filter bit 9 */
#define CAN_F5R1_FB10 0x00000400U /*!<Filter bit 10 */
#define CAN_F5R1_FB11 0x00000800U /*!<Filter bit 11 */
#define CAN_F5R1_FB12 0x00001000U /*!<Filter bit 12 */
#define CAN_F5R1_FB13 0x00002000U /*!<Filter bit 13 */
#define CAN_F5R1_FB14 0x00004000U /*!<Filter bit 14 */
#define CAN_F5R1_FB15 0x00008000U /*!<Filter bit 15 */
#define CAN_F5R1_FB16 0x00010000U /*!<Filter bit 16 */
#define CAN_F5R1_FB17 0x00020000U /*!<Filter bit 17 */
#define CAN_F5R1_FB18 0x00040000U /*!<Filter bit 18 */
#define CAN_F5R1_FB19 0x00080000U /*!<Filter bit 19 */
#define CAN_F5R1_FB20 0x00100000U /*!<Filter bit 20 */
#define CAN_F5R1_FB21 0x00200000U /*!<Filter bit 21 */
#define CAN_F5R1_FB22 0x00400000U /*!<Filter bit 22 */
#define CAN_F5R1_FB23 0x00800000U /*!<Filter bit 23 */
#define CAN_F5R1_FB24 0x01000000U /*!<Filter bit 24 */
#define CAN_F5R1_FB25 0x02000000U /*!<Filter bit 25 */
#define CAN_F5R1_FB26 0x04000000U /*!<Filter bit 26 */
#define CAN_F5R1_FB27 0x08000000U /*!<Filter bit 27 */
#define CAN_F5R1_FB28 0x10000000U /*!<Filter bit 28 */
#define CAN_F5R1_FB29 0x20000000U /*!<Filter bit 29 */
#define CAN_F5R1_FB30 0x40000000U /*!<Filter bit 30 */
#define CAN_F5R1_FB31 0x80000000U /*!<Filter bit 31 */
/******************* Bit definition for CAN_F6R1 register *******************/
#define CAN_F6R1_FB0 0x00000001U /*!<Filter bit 0 */
#define CAN_F6R1_FB1 0x00000002U /*!<Filter bit 1 */
#define CAN_F6R1_FB2 0x00000004U /*!<Filter bit 2 */
#define CAN_F6R1_FB3 0x00000008U /*!<Filter bit 3 */
#define CAN_F6R1_FB4 0x00000010U /*!<Filter bit 4 */
#define CAN_F6R1_FB5 0x00000020U /*!<Filter bit 5 */
#define CAN_F6R1_FB6 0x00000040U /*!<Filter bit 6 */
#define CAN_F6R1_FB7 0x00000080U /*!<Filter bit 7 */
#define CAN_F6R1_FB8 0x00000100U /*!<Filter bit 8 */
#define CAN_F6R1_FB9 0x00000200U /*!<Filter bit 9 */
#define CAN_F6R1_FB10 0x00000400U /*!<Filter bit 10 */
#define CAN_F6R1_FB11 0x00000800U /*!<Filter bit 11 */
#define CAN_F6R1_FB12 0x00001000U /*!<Filter bit 12 */
#define CAN_F6R1_FB13 0x00002000U /*!<Filter bit 13 */
#define CAN_F6R1_FB14 0x00004000U /*!<Filter bit 14 */
#define CAN_F6R1_FB15 0x00008000U /*!<Filter bit 15 */
#define CAN_F6R1_FB16 0x00010000U /*!<Filter bit 16 */
#define CAN_F6R1_FB17 0x00020000U /*!<Filter bit 17 */
#define CAN_F6R1_FB18 0x00040000U /*!<Filter bit 18 */
#define CAN_F6R1_FB19 0x00080000U /*!<Filter bit 19 */
#define CAN_F6R1_FB20 0x00100000U /*!<Filter bit 20 */
#define CAN_F6R1_FB21 0x00200000U /*!<Filter bit 21 */
#define CAN_F6R1_FB22 0x00400000U /*!<Filter bit 22 */
#define CAN_F6R1_FB23 0x00800000U /*!<Filter bit 23 */
#define CAN_F6R1_FB24 0x01000000U /*!<Filter bit 24 */
#define CAN_F6R1_FB25 0x02000000U /*!<Filter bit 25 */
#define CAN_F6R1_FB26 0x04000000U /*!<Filter bit 26 */
#define CAN_F6R1_FB27 0x08000000U /*!<Filter bit 27 */
#define CAN_F6R1_FB28 0x10000000U /*!<Filter bit 28 */
#define CAN_F6R1_FB29 0x20000000U /*!<Filter bit 29 */
#define CAN_F6R1_FB30 0x40000000U /*!<Filter bit 30 */
#define CAN_F6R1_FB31 0x80000000U /*!<Filter bit 31 */
/******************* Bit definition for CAN_F7R1 register *******************/
#define CAN_F7R1_FB0 0x00000001U /*!<Filter bit 0 */
#define CAN_F7R1_FB1 0x00000002U /*!<Filter bit 1 */
#define CAN_F7R1_FB2 0x00000004U /*!<Filter bit 2 */
#define CAN_F7R1_FB3 0x00000008U /*!<Filter bit 3 */
#define CAN_F7R1_FB4 0x00000010U /*!<Filter bit 4 */
#define CAN_F7R1_FB5 0x00000020U /*!<Filter bit 5 */
#define CAN_F7R1_FB6 0x00000040U /*!<Filter bit 6 */
#define CAN_F7R1_FB7 0x00000080U /*!<Filter bit 7 */
#define CAN_F7R1_FB8 0x00000100U /*!<Filter bit 8 */
#define CAN_F7R1_FB9 0x00000200U /*!<Filter bit 9 */
#define CAN_F7R1_FB10 0x00000400U /*!<Filter bit 10 */
#define CAN_F7R1_FB11 0x00000800U /*!<Filter bit 11 */
#define CAN_F7R1_FB12 0x00001000U /*!<Filter bit 12 */
#define CAN_F7R1_FB13 0x00002000U /*!<Filter bit 13 */
#define CAN_F7R1_FB14 0x00004000U /*!<Filter bit 14 */
#define CAN_F7R1_FB15 0x00008000U /*!<Filter bit 15 */
#define CAN_F7R1_FB16 0x00010000U /*!<Filter bit 16 */
#define CAN_F7R1_FB17 0x00020000U /*!<Filter bit 17 */
#define CAN_F7R1_FB18 0x00040000U /*!<Filter bit 18 */
#define CAN_F7R1_FB19 0x00080000U /*!<Filter bit 19 */
#define CAN_F7R1_FB20 0x00100000U /*!<Filter bit 20 */
#define CAN_F7R1_FB21 0x00200000U /*!<Filter bit 21 */
#define CAN_F7R1_FB22 0x00400000U /*!<Filter bit 22 */
#define CAN_F7R1_FB23 0x00800000U /*!<Filter bit 23 */
#define CAN_F7R1_FB24 0x01000000U /*!<Filter bit 24 */
#define CAN_F7R1_FB25 0x02000000U /*!<Filter bit 25 */
#define CAN_F7R1_FB26 0x04000000U /*!<Filter bit 26 */
#define CAN_F7R1_FB27 0x08000000U /*!<Filter bit 27 */
#define CAN_F7R1_FB28 0x10000000U /*!<Filter bit 28 */
#define CAN_F7R1_FB29 0x20000000U /*!<Filter bit 29 */
#define CAN_F7R1_FB30 0x40000000U /*!<Filter bit 30 */
#define CAN_F7R1_FB31 0x80000000U /*!<Filter bit 31 */
/******************* Bit definition for CAN_F8R1 register *******************/
#define CAN_F8R1_FB0 0x00000001U /*!<Filter bit 0 */
#define CAN_F8R1_FB1 0x00000002U /*!<Filter bit 1 */
#define CAN_F8R1_FB2 0x00000004U /*!<Filter bit 2 */
#define CAN_F8R1_FB3 0x00000008U /*!<Filter bit 3 */
#define CAN_F8R1_FB4 0x00000010U /*!<Filter bit 4 */
#define CAN_F8R1_FB5 0x00000020U /*!<Filter bit 5 */
#define CAN_F8R1_FB6 0x00000040U /*!<Filter bit 6 */
#define CAN_F8R1_FB7 0x00000080U /*!<Filter bit 7 */
#define CAN_F8R1_FB8 0x00000100U /*!<Filter bit 8 */
#define CAN_F8R1_FB9 0x00000200U /*!<Filter bit 9 */
#define CAN_F8R1_FB10 0x00000400U /*!<Filter bit 10 */
#define CAN_F8R1_FB11 0x00000800U /*!<Filter bit 11 */
#define CAN_F8R1_FB12 0x00001000U /*!<Filter bit 12 */
#define CAN_F8R1_FB13 0x00002000U /*!<Filter bit 13 */
#define CAN_F8R1_FB14 0x00004000U /*!<Filter bit 14 */
#define CAN_F8R1_FB15 0x00008000U /*!<Filter bit 15 */
#define CAN_F8R1_FB16 0x00010000U /*!<Filter bit 16 */
#define CAN_F8R1_FB17 0x00020000U /*!<Filter bit 17 */
#define CAN_F8R1_FB18 0x00040000U /*!<Filter bit 18 */
#define CAN_F8R1_FB19 0x00080000U /*!<Filter bit 19 */
#define CAN_F8R1_FB20 0x00100000U /*!<Filter bit 20 */
#define CAN_F8R1_FB21 0x00200000U /*!<Filter bit 21 */
#define CAN_F8R1_FB22 0x00400000U /*!<Filter bit 22 */
#define CAN_F8R1_FB23 0x00800000U /*!<Filter bit 23 */
#define CAN_F8R1_FB24 0x01000000U /*!<Filter bit 24 */
#define CAN_F8R1_FB25 0x02000000U /*!<Filter bit 25 */
#define CAN_F8R1_FB26 0x04000000U /*!<Filter bit 26 */
#define CAN_F8R1_FB27 0x08000000U /*!<Filter bit 27 */
#define CAN_F8R1_FB28 0x10000000U /*!<Filter bit 28 */
#define CAN_F8R1_FB29 0x20000000U /*!<Filter bit 29 */
#define CAN_F8R1_FB30 0x40000000U /*!<Filter bit 30 */
#define CAN_F8R1_FB31 0x80000000U /*!<Filter bit 31 */
/******************* Bit definition for CAN_F9R1 register *******************/
#define CAN_F9R1_FB0 0x00000001U /*!<Filter bit 0 */
#define CAN_F9R1_FB1 0x00000002U /*!<Filter bit 1 */
#define CAN_F9R1_FB2 0x00000004U /*!<Filter bit 2 */
#define CAN_F9R1_FB3 0x00000008U /*!<Filter bit 3 */
#define CAN_F9R1_FB4 0x00000010U /*!<Filter bit 4 */
#define CAN_F9R1_FB5 0x00000020U /*!<Filter bit 5 */
#define CAN_F9R1_FB6 0x00000040U /*!<Filter bit 6 */
#define CAN_F9R1_FB7 0x00000080U /*!<Filter bit 7 */
#define CAN_F9R1_FB8 0x00000100U /*!<Filter bit 8 */
#define CAN_F9R1_FB9 0x00000200U /*!<Filter bit 9 */
#define CAN_F9R1_FB10 0x00000400U /*!<Filter bit 10 */
#define CAN_F9R1_FB11 0x00000800U /*!<Filter bit 11 */
#define CAN_F9R1_FB12 0x00001000U /*!<Filter bit 12 */
#define CAN_F9R1_FB13 0x00002000U /*!<Filter bit 13 */
#define CAN_F9R1_FB14 0x00004000U /*!<Filter bit 14 */
#define CAN_F9R1_FB15 0x00008000U /*!<Filter bit 15 */
#define CAN_F9R1_FB16 0x00010000U /*!<Filter bit 16 */
#define CAN_F9R1_FB17 0x00020000U /*!<Filter bit 17 */
#define CAN_F9R1_FB18 0x00040000U /*!<Filter bit 18 */
#define CAN_F9R1_FB19 0x00080000U /*!<Filter bit 19 */
#define CAN_F9R1_FB20 0x00100000U /*!<Filter bit 20 */
#define CAN_F9R1_FB21 0x00200000U /*!<Filter bit 21 */
#define CAN_F9R1_FB22 0x00400000U /*!<Filter bit 22 */
#define CAN_F9R1_FB23 0x00800000U /*!<Filter bit 23 */
#define CAN_F9R1_FB24 0x01000000U /*!<Filter bit 24 */
#define CAN_F9R1_FB25 0x02000000U /*!<Filter bit 25 */
#define CAN_F9R1_FB26 0x04000000U /*!<Filter bit 26 */
#define CAN_F9R1_FB27 0x08000000U /*!<Filter bit 27 */
#define CAN_F9R1_FB28 0x10000000U /*!<Filter bit 28 */
#define CAN_F9R1_FB29 0x20000000U /*!<Filter bit 29 */
#define CAN_F9R1_FB30 0x40000000U /*!<Filter bit 30 */
#define CAN_F9R1_FB31 0x80000000U /*!<Filter bit 31 */
/******************* Bit definition for CAN_F10R1 register ******************/
#define CAN_F10R1_FB0 0x00000001U /*!<Filter bit 0 */
#define CAN_F10R1_FB1 0x00000002U /*!<Filter bit 1 */
#define CAN_F10R1_FB2 0x00000004U /*!<Filter bit 2 */
#define CAN_F10R1_FB3 0x00000008U /*!<Filter bit 3 */
#define CAN_F10R1_FB4 0x00000010U /*!<Filter bit 4 */
#define CAN_F10R1_FB5 0x00000020U /*!<Filter bit 5 */
#define CAN_F10R1_FB6 0x00000040U /*!<Filter bit 6 */
#define CAN_F10R1_FB7 0x00000080U /*!<Filter bit 7 */
#define CAN_F10R1_FB8 0x00000100U /*!<Filter bit 8 */
#define CAN_F10R1_FB9 0x00000200U /*!<Filter bit 9 */
#define CAN_F10R1_FB10 0x00000400U /*!<Filter bit 10 */
#define CAN_F10R1_FB11 0x00000800U /*!<Filter bit 11 */
#define CAN_F10R1_FB12 0x00001000U /*!<Filter bit 12 */
#define CAN_F10R1_FB13 0x00002000U /*!<Filter bit 13 */
#define CAN_F10R1_FB14 0x00004000U /*!<Filter bit 14 */
#define CAN_F10R1_FB15 0x00008000U /*!<Filter bit 15 */
#define CAN_F10R1_FB16 0x00010000U /*!<Filter bit 16 */
#define CAN_F10R1_FB17 0x00020000U /*!<Filter bit 17 */
#define CAN_F10R1_FB18 0x00040000U /*!<Filter bit 18 */
#define CAN_F10R1_FB19 0x00080000U /*!<Filter bit 19 */
#define CAN_F10R1_FB20 0x00100000U /*!<Filter bit 20 */
#define CAN_F10R1_FB21 0x00200000U /*!<Filter bit 21 */
#define CAN_F10R1_FB22 0x00400000U /*!<Filter bit 22 */
#define CAN_F10R1_FB23 0x00800000U /*!<Filter bit 23 */
#define CAN_F10R1_FB24 0x01000000U /*!<Filter bit 24 */
#define CAN_F10R1_FB25 0x02000000U /*!<Filter bit 25 */
#define CAN_F10R1_FB26 0x04000000U /*!<Filter bit 26 */
#define CAN_F10R1_FB27 0x08000000U /*!<Filter bit 27 */
#define CAN_F10R1_FB28 0x10000000U /*!<Filter bit 28 */
#define CAN_F10R1_FB29 0x20000000U /*!<Filter bit 29 */
#define CAN_F10R1_FB30 0x40000000U /*!<Filter bit 30 */
#define CAN_F10R1_FB31 0x80000000U /*!<Filter bit 31 */
/******************* Bit definition for CAN_F11R1 register ******************/
#define CAN_F11R1_FB0 0x00000001U /*!<Filter bit 0 */
#define CAN_F11R1_FB1 0x00000002U /*!<Filter bit 1 */
#define CAN_F11R1_FB2 0x00000004U /*!<Filter bit 2 */
#define CAN_F11R1_FB3 0x00000008U /*!<Filter bit 3 */
#define CAN_F11R1_FB4 0x00000010U /*!<Filter bit 4 */
#define CAN_F11R1_FB5 0x00000020U /*!<Filter bit 5 */
#define CAN_F11R1_FB6 0x00000040U /*!<Filter bit 6 */
#define CAN_F11R1_FB7 0x00000080U /*!<Filter bit 7 */
#define CAN_F11R1_FB8 0x00000100U /*!<Filter bit 8 */
#define CAN_F11R1_FB9 0x00000200U /*!<Filter bit 9 */
#define CAN_F11R1_FB10 0x00000400U /*!<Filter bit 10 */
#define CAN_F11R1_FB11 0x00000800U /*!<Filter bit 11 */
#define CAN_F11R1_FB12 0x00001000U /*!<Filter bit 12 */
#define CAN_F11R1_FB13 0x00002000U /*!<Filter bit 13 */
#define CAN_F11R1_FB14 0x00004000U /*!<Filter bit 14 */
#define CAN_F11R1_FB15 0x00008000U /*!<Filter bit 15 */
#define CAN_F11R1_FB16 0x00010000U /*!<Filter bit 16 */
#define CAN_F11R1_FB17 0x00020000U /*!<Filter bit 17 */
#define CAN_F11R1_FB18 0x00040000U /*!<Filter bit 18 */
#define CAN_F11R1_FB19 0x00080000U /*!<Filter bit 19 */
#define CAN_F11R1_FB20 0x00100000U /*!<Filter bit 20 */
#define CAN_F11R1_FB21 0x00200000U /*!<Filter bit 21 */
#define CAN_F11R1_FB22 0x00400000U /*!<Filter bit 22 */
#define CAN_F11R1_FB23 0x00800000U /*!<Filter bit 23 */
#define CAN_F11R1_FB24 0x01000000U /*!<Filter bit 24 */
#define CAN_F11R1_FB25 0x02000000U /*!<Filter bit 25 */
#define CAN_F11R1_FB26 0x04000000U /*!<Filter bit 26 */
#define CAN_F11R1_FB27 0x08000000U /*!<Filter bit 27 */
#define CAN_F11R1_FB28 0x10000000U /*!<Filter bit 28 */
#define CAN_F11R1_FB29 0x20000000U /*!<Filter bit 29 */
#define CAN_F11R1_FB30 0x40000000U /*!<Filter bit 30 */
#define CAN_F11R1_FB31 0x80000000U /*!<Filter bit 31 */
/******************* Bit definition for CAN_F12R1 register ******************/
#define CAN_F12R1_FB0 0x00000001U /*!<Filter bit 0 */
#define CAN_F12R1_FB1 0x00000002U /*!<Filter bit 1 */
#define CAN_F12R1_FB2 0x00000004U /*!<Filter bit 2 */
#define CAN_F12R1_FB3 0x00000008U /*!<Filter bit 3 */
#define CAN_F12R1_FB4 0x00000010U /*!<Filter bit 4 */
#define CAN_F12R1_FB5 0x00000020U /*!<Filter bit 5 */
#define CAN_F12R1_FB6 0x00000040U /*!<Filter bit 6 */
#define CAN_F12R1_FB7 0x00000080U /*!<Filter bit 7 */
#define CAN_F12R1_FB8 0x00000100U /*!<Filter bit 8 */
#define CAN_F12R1_FB9 0x00000200U /*!<Filter bit 9 */
#define CAN_F12R1_FB10 0x00000400U /*!<Filter bit 10 */
#define CAN_F12R1_FB11 0x00000800U /*!<Filter bit 11 */
#define CAN_F12R1_FB12 0x00001000U /*!<Filter bit 12 */
#define CAN_F12R1_FB13 0x00002000U /*!<Filter bit 13 */
#define CAN_F12R1_FB14 0x00004000U /*!<Filter bit 14 */
#define CAN_F12R1_FB15 0x00008000U /*!<Filter bit 15 */
#define CAN_F12R1_FB16 0x00010000U /*!<Filter bit 16 */
#define CAN_F12R1_FB17 0x00020000U /*!<Filter bit 17 */
#define CAN_F12R1_FB18 0x00040000U /*!<Filter bit 18 */
#define CAN_F12R1_FB19 0x00080000U /*!<Filter bit 19 */
#define CAN_F12R1_FB20 0x00100000U /*!<Filter bit 20 */
#define CAN_F12R1_FB21 0x00200000U /*!<Filter bit 21 */
#define CAN_F12R1_FB22 0x00400000U /*!<Filter bit 22 */
#define CAN_F12R1_FB23 0x00800000U /*!<Filter bit 23 */
#define CAN_F12R1_FB24 0x01000000U /*!<Filter bit 24 */
#define CAN_F12R1_FB25 0x02000000U /*!<Filter bit 25 */
#define CAN_F12R1_FB26 0x04000000U /*!<Filter bit 26 */
#define CAN_F12R1_FB27 0x08000000U /*!<Filter bit 27 */
#define CAN_F12R1_FB28 0x10000000U /*!<Filter bit 28 */
#define CAN_F12R1_FB29 0x20000000U /*!<Filter bit 29 */
#define CAN_F12R1_FB30 0x40000000U /*!<Filter bit 30 */
#define CAN_F12R1_FB31 0x80000000U /*!<Filter bit 31 */
/******************* Bit definition for CAN_F13R1 register ******************/
#define CAN_F13R1_FB0 0x00000001U /*!<Filter bit 0 */
#define CAN_F13R1_FB1 0x00000002U /*!<Filter bit 1 */
#define CAN_F13R1_FB2 0x00000004U /*!<Filter bit 2 */
#define CAN_F13R1_FB3 0x00000008U /*!<Filter bit 3 */
#define CAN_F13R1_FB4 0x00000010U /*!<Filter bit 4 */
#define CAN_F13R1_FB5 0x00000020U /*!<Filter bit 5 */
#define CAN_F13R1_FB6 0x00000040U /*!<Filter bit 6 */
#define CAN_F13R1_FB7 0x00000080U /*!<Filter bit 7 */
#define CAN_F13R1_FB8 0x00000100U /*!<Filter bit 8 */
#define CAN_F13R1_FB9 0x00000200U /*!<Filter bit 9 */
#define CAN_F13R1_FB10 0x00000400U /*!<Filter bit 10 */
#define CAN_F13R1_FB11 0x00000800U /*!<Filter bit 11 */
#define CAN_F13R1_FB12 0x00001000U /*!<Filter bit 12 */
#define CAN_F13R1_FB13 0x00002000U /*!<Filter bit 13 */
#define CAN_F13R1_FB14 0x00004000U /*!<Filter bit 14 */
#define CAN_F13R1_FB15 0x00008000U /*!<Filter bit 15 */
#define CAN_F13R1_FB16 0x00010000U /*!<Filter bit 16 */
#define CAN_F13R1_FB17 0x00020000U /*!<Filter bit 17 */
#define CAN_F13R1_FB18 0x00040000U /*!<Filter bit 18 */
#define CAN_F13R1_FB19 0x00080000U /*!<Filter bit 19 */
#define CAN_F13R1_FB20 0x00100000U /*!<Filter bit 20 */
#define CAN_F13R1_FB21 0x00200000U /*!<Filter bit 21 */
#define CAN_F13R1_FB22 0x00400000U /*!<Filter bit 22 */
#define CAN_F13R1_FB23 0x00800000U /*!<Filter bit 23 */
#define CAN_F13R1_FB24 0x01000000U /*!<Filter bit 24 */
#define CAN_F13R1_FB25 0x02000000U /*!<Filter bit 25 */
#define CAN_F13R1_FB26 0x04000000U /*!<Filter bit 26 */
#define CAN_F13R1_FB27 0x08000000U /*!<Filter bit 27 */
#define CAN_F13R1_FB28 0x10000000U /*!<Filter bit 28 */
#define CAN_F13R1_FB29 0x20000000U /*!<Filter bit 29 */
#define CAN_F13R1_FB30 0x40000000U /*!<Filter bit 30 */
#define CAN_F13R1_FB31 0x80000000U /*!<Filter bit 31 */
/******************* Bit definition for CAN_F0R2 register *******************/
#define CAN_F0R2_FB0 0x00000001U /*!<Filter bit 0 */
#define CAN_F0R2_FB1 0x00000002U /*!<Filter bit 1 */
#define CAN_F0R2_FB2 0x00000004U /*!<Filter bit 2 */
#define CAN_F0R2_FB3 0x00000008U /*!<Filter bit 3 */
#define CAN_F0R2_FB4 0x00000010U /*!<Filter bit 4 */
#define CAN_F0R2_FB5 0x00000020U /*!<Filter bit 5 */
#define CAN_F0R2_FB6 0x00000040U /*!<Filter bit 6 */
#define CAN_F0R2_FB7 0x00000080U /*!<Filter bit 7 */
#define CAN_F0R2_FB8 0x00000100U /*!<Filter bit 8 */
#define CAN_F0R2_FB9 0x00000200U /*!<Filter bit 9 */
#define CAN_F0R2_FB10 0x00000400U /*!<Filter bit 10 */
#define CAN_F0R2_FB11 0x00000800U /*!<Filter bit 11 */
#define CAN_F0R2_FB12 0x00001000U /*!<Filter bit 12 */
#define CAN_F0R2_FB13 0x00002000U /*!<Filter bit 13 */
#define CAN_F0R2_FB14 0x00004000U /*!<Filter bit 14 */
#define CAN_F0R2_FB15 0x00008000U /*!<Filter bit 15 */
#define CAN_F0R2_FB16 0x00010000U /*!<Filter bit 16 */
#define CAN_F0R2_FB17 0x00020000U /*!<Filter bit 17 */
#define CAN_F0R2_FB18 0x00040000U /*!<Filter bit 18 */
#define CAN_F0R2_FB19 0x00080000U /*!<Filter bit 19 */
#define CAN_F0R2_FB20 0x00100000U /*!<Filter bit 20 */
#define CAN_F0R2_FB21 0x00200000U /*!<Filter bit 21 */
#define CAN_F0R2_FB22 0x00400000U /*!<Filter bit 22 */
#define CAN_F0R2_FB23 0x00800000U /*!<Filter bit 23 */
#define CAN_F0R2_FB24 0x01000000U /*!<Filter bit 24 */
#define CAN_F0R2_FB25 0x02000000U /*!<Filter bit 25 */
#define CAN_F0R2_FB26 0x04000000U /*!<Filter bit 26 */
#define CAN_F0R2_FB27 0x08000000U /*!<Filter bit 27 */
#define CAN_F0R2_FB28 0x10000000U /*!<Filter bit 28 */
#define CAN_F0R2_FB29 0x20000000U /*!<Filter bit 29 */
#define CAN_F0R2_FB30 0x40000000U /*!<Filter bit 30 */
#define CAN_F0R2_FB31 0x80000000U /*!<Filter bit 31 */
/******************* Bit definition for CAN_F1R2 register *******************/
#define CAN_F1R2_FB0 0x00000001U /*!<Filter bit 0 */
#define CAN_F1R2_FB1 0x00000002U /*!<Filter bit 1 */
#define CAN_F1R2_FB2 0x00000004U /*!<Filter bit 2 */
#define CAN_F1R2_FB3 0x00000008U /*!<Filter bit 3 */
#define CAN_F1R2_FB4 0x00000010U /*!<Filter bit 4 */
#define CAN_F1R2_FB5 0x00000020U /*!<Filter bit 5 */
#define CAN_F1R2_FB6 0x00000040U /*!<Filter bit 6 */
#define CAN_F1R2_FB7 0x00000080U /*!<Filter bit 7 */
#define CAN_F1R2_FB8 0x00000100U /*!<Filter bit 8 */
#define CAN_F1R2_FB9 0x00000200U /*!<Filter bit 9 */
#define CAN_F1R2_FB10 0x00000400U /*!<Filter bit 10 */
#define CAN_F1R2_FB11 0x00000800U /*!<Filter bit 11 */
#define CAN_F1R2_FB12 0x00001000U /*!<Filter bit 12 */
#define CAN_F1R2_FB13 0x00002000U /*!<Filter bit 13 */
#define CAN_F1R2_FB14 0x00004000U /*!<Filter bit 14 */
#define CAN_F1R2_FB15 0x00008000U /*!<Filter bit 15 */
#define CAN_F1R2_FB16 0x00010000U /*!<Filter bit 16 */
#define CAN_F1R2_FB17 0x00020000U /*!<Filter bit 17 */
#define CAN_F1R2_FB18 0x00040000U /*!<Filter bit 18 */
#define CAN_F1R2_FB19 0x00080000U /*!<Filter bit 19 */
#define CAN_F1R2_FB20 0x00100000U /*!<Filter bit 20 */
#define CAN_F1R2_FB21 0x00200000U /*!<Filter bit 21 */
#define CAN_F1R2_FB22 0x00400000U /*!<Filter bit 22 */
#define CAN_F1R2_FB23 0x00800000U /*!<Filter bit 23 */
#define CAN_F1R2_FB24 0x01000000U /*!<Filter bit 24 */
#define CAN_F1R2_FB25 0x02000000U /*!<Filter bit 25 */
#define CAN_F1R2_FB26 0x04000000U /*!<Filter bit 26 */
#define CAN_F1R2_FB27 0x08000000U /*!<Filter bit 27 */
#define CAN_F1R2_FB28 0x10000000U /*!<Filter bit 28 */
#define CAN_F1R2_FB29 0x20000000U /*!<Filter bit 29 */
#define CAN_F1R2_FB30 0x40000000U /*!<Filter bit 30 */
#define CAN_F1R2_FB31 0x80000000U /*!<Filter bit 31 */
/******************* Bit definition for CAN_F2R2 register *******************/
#define CAN_F2R2_FB0 0x00000001U /*!<Filter bit 0 */
#define CAN_F2R2_FB1 0x00000002U /*!<Filter bit 1 */
#define CAN_F2R2_FB2 0x00000004U /*!<Filter bit 2 */
#define CAN_F2R2_FB3 0x00000008U /*!<Filter bit 3 */
#define CAN_F2R2_FB4 0x00000010U /*!<Filter bit 4 */
#define CAN_F2R2_FB5 0x00000020U /*!<Filter bit 5 */
#define CAN_F2R2_FB6 0x00000040U /*!<Filter bit 6 */
#define CAN_F2R2_FB7 0x00000080U /*!<Filter bit 7 */
#define CAN_F2R2_FB8 0x00000100U /*!<Filter bit 8 */
#define CAN_F2R2_FB9 0x00000200U /*!<Filter bit 9 */
#define CAN_F2R2_FB10 0x00000400U /*!<Filter bit 10 */
#define CAN_F2R2_FB11 0x00000800U /*!<Filter bit 11 */
#define CAN_F2R2_FB12 0x00001000U /*!<Filter bit 12 */
#define CAN_F2R2_FB13 0x00002000U /*!<Filter bit 13 */
#define CAN_F2R2_FB14 0x00004000U /*!<Filter bit 14 */
#define CAN_F2R2_FB15 0x00008000U /*!<Filter bit 15 */
#define CAN_F2R2_FB16 0x00010000U /*!<Filter bit 16 */
#define CAN_F2R2_FB17 0x00020000U /*!<Filter bit 17 */
#define CAN_F2R2_FB18 0x00040000U /*!<Filter bit 18 */
#define CAN_F2R2_FB19 0x00080000U /*!<Filter bit 19 */
#define CAN_F2R2_FB20 0x00100000U /*!<Filter bit 20 */
#define CAN_F2R2_FB21 0x00200000U /*!<Filter bit 21 */
#define CAN_F2R2_FB22 0x00400000U /*!<Filter bit 22 */
#define CAN_F2R2_FB23 0x00800000U /*!<Filter bit 23 */
#define CAN_F2R2_FB24 0x01000000U /*!<Filter bit 24 */
#define CAN_F2R2_FB25 0x02000000U /*!<Filter bit 25 */
#define CAN_F2R2_FB26 0x04000000U /*!<Filter bit 26 */
#define CAN_F2R2_FB27 0x08000000U /*!<Filter bit 27 */
#define CAN_F2R2_FB28 0x10000000U /*!<Filter bit 28 */
#define CAN_F2R2_FB29 0x20000000U /*!<Filter bit 29 */
#define CAN_F2R2_FB30 0x40000000U /*!<Filter bit 30 */
#define CAN_F2R2_FB31 0x80000000U /*!<Filter bit 31 */
/******************* Bit definition for CAN_F3R2 register *******************/
#define CAN_F3R2_FB0 0x00000001U /*!<Filter bit 0 */
#define CAN_F3R2_FB1 0x00000002U /*!<Filter bit 1 */
#define CAN_F3R2_FB2 0x00000004U /*!<Filter bit 2 */
#define CAN_F3R2_FB3 0x00000008U /*!<Filter bit 3 */
#define CAN_F3R2_FB4 0x00000010U /*!<Filter bit 4 */
#define CAN_F3R2_FB5 0x00000020U /*!<Filter bit 5 */
#define CAN_F3R2_FB6 0x00000040U /*!<Filter bit 6 */
#define CAN_F3R2_FB7 0x00000080U /*!<Filter bit 7 */
#define CAN_F3R2_FB8 0x00000100U /*!<Filter bit 8 */
#define CAN_F3R2_FB9 0x00000200U /*!<Filter bit 9 */
#define CAN_F3R2_FB10 0x00000400U /*!<Filter bit 10 */
#define CAN_F3R2_FB11 0x00000800U /*!<Filter bit 11 */
#define CAN_F3R2_FB12 0x00001000U /*!<Filter bit 12 */
#define CAN_F3R2_FB13 0x00002000U /*!<Filter bit 13 */
#define CAN_F3R2_FB14 0x00004000U /*!<Filter bit 14 */
#define CAN_F3R2_FB15 0x00008000U /*!<Filter bit 15 */
#define CAN_F3R2_FB16 0x00010000U /*!<Filter bit 16 */
#define CAN_F3R2_FB17 0x00020000U /*!<Filter bit 17 */
#define CAN_F3R2_FB18 0x00040000U /*!<Filter bit 18 */
#define CAN_F3R2_FB19 0x00080000U /*!<Filter bit 19 */
#define CAN_F3R2_FB20 0x00100000U /*!<Filter bit 20 */
#define CAN_F3R2_FB21 0x00200000U /*!<Filter bit 21 */
#define CAN_F3R2_FB22 0x00400000U /*!<Filter bit 22 */
#define CAN_F3R2_FB23 0x00800000U /*!<Filter bit 23 */
#define CAN_F3R2_FB24 0x01000000U /*!<Filter bit 24 */
#define CAN_F3R2_FB25 0x02000000U /*!<Filter bit 25 */
#define CAN_F3R2_FB26 0x04000000U /*!<Filter bit 26 */
#define CAN_F3R2_FB27 0x08000000U /*!<Filter bit 27 */
#define CAN_F3R2_FB28 0x10000000U /*!<Filter bit 28 */
#define CAN_F3R2_FB29 0x20000000U /*!<Filter bit 29 */
#define CAN_F3R2_FB30 0x40000000U /*!<Filter bit 30 */
#define CAN_F3R2_FB31 0x80000000U /*!<Filter bit 31 */
/******************* Bit definition for CAN_F4R2 register *******************/
#define CAN_F4R2_FB0 0x00000001U /*!<Filter bit 0 */
#define CAN_F4R2_FB1 0x00000002U /*!<Filter bit 1 */
#define CAN_F4R2_FB2 0x00000004U /*!<Filter bit 2 */
#define CAN_F4R2_FB3 0x00000008U /*!<Filter bit 3 */
#define CAN_F4R2_FB4 0x00000010U /*!<Filter bit 4 */
#define CAN_F4R2_FB5 0x00000020U /*!<Filter bit 5 */
#define CAN_F4R2_FB6 0x00000040U /*!<Filter bit 6 */
#define CAN_F4R2_FB7 0x00000080U /*!<Filter bit 7 */
#define CAN_F4R2_FB8 0x00000100U /*!<Filter bit 8 */
#define CAN_F4R2_FB9 0x00000200U /*!<Filter bit 9 */
#define CAN_F4R2_FB10 0x00000400U /*!<Filter bit 10 */
#define CAN_F4R2_FB11 0x00000800U /*!<Filter bit 11 */
#define CAN_F4R2_FB12 0x00001000U /*!<Filter bit 12 */
#define CAN_F4R2_FB13 0x00002000U /*!<Filter bit 13 */
#define CAN_F4R2_FB14 0x00004000U /*!<Filter bit 14 */
#define CAN_F4R2_FB15 0x00008000U /*!<Filter bit 15 */
#define CAN_F4R2_FB16 0x00010000U /*!<Filter bit 16 */
#define CAN_F4R2_FB17 0x00020000U /*!<Filter bit 17 */
#define CAN_F4R2_FB18 0x00040000U /*!<Filter bit 18 */
#define CAN_F4R2_FB19 0x00080000U /*!<Filter bit 19 */
#define CAN_F4R2_FB20 0x00100000U /*!<Filter bit 20 */
#define CAN_F4R2_FB21 0x00200000U /*!<Filter bit 21 */
#define CAN_F4R2_FB22 0x00400000U /*!<Filter bit 22 */
#define CAN_F4R2_FB23 0x00800000U /*!<Filter bit 23 */
#define CAN_F4R2_FB24 0x01000000U /*!<Filter bit 24 */
#define CAN_F4R2_FB25 0x02000000U /*!<Filter bit 25 */
#define CAN_F4R2_FB26 0x04000000U /*!<Filter bit 26 */
#define CAN_F4R2_FB27 0x08000000U /*!<Filter bit 27 */
#define CAN_F4R2_FB28 0x10000000U /*!<Filter bit 28 */
#define CAN_F4R2_FB29 0x20000000U /*!<Filter bit 29 */
#define CAN_F4R2_FB30 0x40000000U /*!<Filter bit 30 */
#define CAN_F4R2_FB31 0x80000000U /*!<Filter bit 31 */
/******************* Bit definition for CAN_F5R2 register *******************/
#define CAN_F5R2_FB0 0x00000001U /*!<Filter bit 0 */
#define CAN_F5R2_FB1 0x00000002U /*!<Filter bit 1 */
#define CAN_F5R2_FB2 0x00000004U /*!<Filter bit 2 */
#define CAN_F5R2_FB3 0x00000008U /*!<Filter bit 3 */
#define CAN_F5R2_FB4 0x00000010U /*!<Filter bit 4 */
#define CAN_F5R2_FB5 0x00000020U /*!<Filter bit 5 */
#define CAN_F5R2_FB6 0x00000040U /*!<Filter bit 6 */
#define CAN_F5R2_FB7 0x00000080U /*!<Filter bit 7 */
#define CAN_F5R2_FB8 0x00000100U /*!<Filter bit 8 */
#define CAN_F5R2_FB9 0x00000200U /*!<Filter bit 9 */
#define CAN_F5R2_FB10 0x00000400U /*!<Filter bit 10 */
#define CAN_F5R2_FB11 0x00000800U /*!<Filter bit 11 */
#define CAN_F5R2_FB12 0x00001000U /*!<Filter bit 12 */
#define CAN_F5R2_FB13 0x00002000U /*!<Filter bit 13 */
#define CAN_F5R2_FB14 0x00004000U /*!<Filter bit 14 */
#define CAN_F5R2_FB15 0x00008000U /*!<Filter bit 15 */
#define CAN_F5R2_FB16 0x00010000U /*!<Filter bit 16 */
#define CAN_F5R2_FB17 0x00020000U /*!<Filter bit 17 */
#define CAN_F5R2_FB18 0x00040000U /*!<Filter bit 18 */
#define CAN_F5R2_FB19 0x00080000U /*!<Filter bit 19 */
#define CAN_F5R2_FB20 0x00100000U /*!<Filter bit 20 */
#define CAN_F5R2_FB21 0x00200000U /*!<Filter bit 21 */
#define CAN_F5R2_FB22 0x00400000U /*!<Filter bit 22 */
#define CAN_F5R2_FB23 0x00800000U /*!<Filter bit 23 */
#define CAN_F5R2_FB24 0x01000000U /*!<Filter bit 24 */
#define CAN_F5R2_FB25 0x02000000U /*!<Filter bit 25 */
#define CAN_F5R2_FB26 0x04000000U /*!<Filter bit 26 */
#define CAN_F5R2_FB27 0x08000000U /*!<Filter bit 27 */
#define CAN_F5R2_FB28 0x10000000U /*!<Filter bit 28 */
#define CAN_F5R2_FB29 0x20000000U /*!<Filter bit 29 */
#define CAN_F5R2_FB30 0x40000000U /*!<Filter bit 30 */
#define CAN_F5R2_FB31 0x80000000U /*!<Filter bit 31 */
/******************* Bit definition for CAN_F6R2 register *******************/
#define CAN_F6R2_FB0 0x00000001U /*!<Filter bit 0 */
#define CAN_F6R2_FB1 0x00000002U /*!<Filter bit 1 */
#define CAN_F6R2_FB2 0x00000004U /*!<Filter bit 2 */
#define CAN_F6R2_FB3 0x00000008U /*!<Filter bit 3 */
#define CAN_F6R2_FB4 0x00000010U /*!<Filter bit 4 */
#define CAN_F6R2_FB5 0x00000020U /*!<Filter bit 5 */
#define CAN_F6R2_FB6 0x00000040U /*!<Filter bit 6 */
#define CAN_F6R2_FB7 0x00000080U /*!<Filter bit 7 */
#define CAN_F6R2_FB8 0x00000100U /*!<Filter bit 8 */
#define CAN_F6R2_FB9 0x00000200U /*!<Filter bit 9 */
#define CAN_F6R2_FB10 0x00000400U /*!<Filter bit 10 */
#define CAN_F6R2_FB11 0x00000800U /*!<Filter bit 11 */
#define CAN_F6R2_FB12 0x00001000U /*!<Filter bit 12 */
#define CAN_F6R2_FB13 0x00002000U /*!<Filter bit 13 */
#define CAN_F6R2_FB14 0x00004000U /*!<Filter bit 14 */
#define CAN_F6R2_FB15 0x00008000U /*!<Filter bit 15 */
#define CAN_F6R2_FB16 0x00010000U /*!<Filter bit 16 */
#define CAN_F6R2_FB17 0x00020000U /*!<Filter bit 17 */
#define CAN_F6R2_FB18 0x00040000U /*!<Filter bit 18 */
#define CAN_F6R2_FB19 0x00080000U /*!<Filter bit 19 */
#define CAN_F6R2_FB20 0x00100000U /*!<Filter bit 20 */
#define CAN_F6R2_FB21 0x00200000U /*!<Filter bit 21 */
#define CAN_F6R2_FB22 0x00400000U /*!<Filter bit 22 */
#define CAN_F6R2_FB23 0x00800000U /*!<Filter bit 23 */
#define CAN_F6R2_FB24 0x01000000U /*!<Filter bit 24 */
#define CAN_F6R2_FB25 0x02000000U /*!<Filter bit 25 */
#define CAN_F6R2_FB26 0x04000000U /*!<Filter bit 26 */
#define CAN_F6R2_FB27 0x08000000U /*!<Filter bit 27 */
#define CAN_F6R2_FB28 0x10000000U /*!<Filter bit 28 */
#define CAN_F6R2_FB29 0x20000000U /*!<Filter bit 29 */
#define CAN_F6R2_FB30 0x40000000U /*!<Filter bit 30 */
#define CAN_F6R2_FB31 0x80000000U /*!<Filter bit 31 */
/******************* Bit definition for CAN_F7R2 register *******************/
#define CAN_F7R2_FB0 0x00000001U /*!<Filter bit 0 */
#define CAN_F7R2_FB1 0x00000002U /*!<Filter bit 1 */
#define CAN_F7R2_FB2 0x00000004U /*!<Filter bit 2 */
#define CAN_F7R2_FB3 0x00000008U /*!<Filter bit 3 */
#define CAN_F7R2_FB4 0x00000010U /*!<Filter bit 4 */
#define CAN_F7R2_FB5 0x00000020U /*!<Filter bit 5 */
#define CAN_F7R2_FB6 0x00000040U /*!<Filter bit 6 */
#define CAN_F7R2_FB7 0x00000080U /*!<Filter bit 7 */
#define CAN_F7R2_FB8 0x00000100U /*!<Filter bit 8 */
#define CAN_F7R2_FB9 0x00000200U /*!<Filter bit 9 */
#define CAN_F7R2_FB10 0x00000400U /*!<Filter bit 10 */
#define CAN_F7R2_FB11 0x00000800U /*!<Filter bit 11 */
#define CAN_F7R2_FB12 0x00001000U /*!<Filter bit 12 */
#define CAN_F7R2_FB13 0x00002000U /*!<Filter bit 13 */
#define CAN_F7R2_FB14 0x00004000U /*!<Filter bit 14 */
#define CAN_F7R2_FB15 0x00008000U /*!<Filter bit 15 */
#define CAN_F7R2_FB16 0x00010000U /*!<Filter bit 16 */
#define CAN_F7R2_FB17 0x00020000U /*!<Filter bit 17 */
#define CAN_F7R2_FB18 0x00040000U /*!<Filter bit 18 */
#define CAN_F7R2_FB19 0x00080000U /*!<Filter bit 19 */
#define CAN_F7R2_FB20 0x00100000U /*!<Filter bit 20 */
#define CAN_F7R2_FB21 0x00200000U /*!<Filter bit 21 */
#define CAN_F7R2_FB22 0x00400000U /*!<Filter bit 22 */
#define CAN_F7R2_FB23 0x00800000U /*!<Filter bit 23 */
#define CAN_F7R2_FB24 0x01000000U /*!<Filter bit 24 */
#define CAN_F7R2_FB25 0x02000000U /*!<Filter bit 25 */
#define CAN_F7R2_FB26 0x04000000U /*!<Filter bit 26 */
#define CAN_F7R2_FB27 0x08000000U /*!<Filter bit 27 */
#define CAN_F7R2_FB28 0x10000000U /*!<Filter bit 28 */
#define CAN_F7R2_FB29 0x20000000U /*!<Filter bit 29 */
#define CAN_F7R2_FB30 0x40000000U /*!<Filter bit 30 */
#define CAN_F7R2_FB31 0x80000000U /*!<Filter bit 31 */
/******************* Bit definition for CAN_F8R2 register *******************/
#define CAN_F8R2_FB0 0x00000001U /*!<Filter bit 0 */
#define CAN_F8R2_FB1 0x00000002U /*!<Filter bit 1 */
#define CAN_F8R2_FB2 0x00000004U /*!<Filter bit 2 */
#define CAN_F8R2_FB3 0x00000008U /*!<Filter bit 3 */
#define CAN_F8R2_FB4 0x00000010U /*!<Filter bit 4 */
#define CAN_F8R2_FB5 0x00000020U /*!<Filter bit 5 */
#define CAN_F8R2_FB6 0x00000040U /*!<Filter bit 6 */
#define CAN_F8R2_FB7 0x00000080U /*!<Filter bit 7 */
#define CAN_F8R2_FB8 0x00000100U /*!<Filter bit 8 */
#define CAN_F8R2_FB9 0x00000200U /*!<Filter bit 9 */
#define CAN_F8R2_FB10 0x00000400U /*!<Filter bit 10 */
#define CAN_F8R2_FB11 0x00000800U /*!<Filter bit 11 */
#define CAN_F8R2_FB12 0x00001000U /*!<Filter bit 12 */
#define CAN_F8R2_FB13 0x00002000U /*!<Filter bit 13 */
#define CAN_F8R2_FB14 0x00004000U /*!<Filter bit 14 */
#define CAN_F8R2_FB15 0x00008000U /*!<Filter bit 15 */
#define CAN_F8R2_FB16 0x00010000U /*!<Filter bit 16 */
#define CAN_F8R2_FB17 0x00020000U /*!<Filter bit 17 */
#define CAN_F8R2_FB18 0x00040000U /*!<Filter bit 18 */
#define CAN_F8R2_FB19 0x00080000U /*!<Filter bit 19 */
#define CAN_F8R2_FB20 0x00100000U /*!<Filter bit 20 */
#define CAN_F8R2_FB21 0x00200000U /*!<Filter bit 21 */
#define CAN_F8R2_FB22 0x00400000U /*!<Filter bit 22 */
#define CAN_F8R2_FB23 0x00800000U /*!<Filter bit 23 */
#define CAN_F8R2_FB24 0x01000000U /*!<Filter bit 24 */
#define CAN_F8R2_FB25 0x02000000U /*!<Filter bit 25 */
#define CAN_F8R2_FB26 0x04000000U /*!<Filter bit 26 */
#define CAN_F8R2_FB27 0x08000000U /*!<Filter bit 27 */
#define CAN_F8R2_FB28 0x10000000U /*!<Filter bit 28 */
#define CAN_F8R2_FB29 0x20000000U /*!<Filter bit 29 */
#define CAN_F8R2_FB30 0x40000000U /*!<Filter bit 30 */
#define CAN_F8R2_FB31 0x80000000U /*!<Filter bit 31 */
/******************* Bit definition for CAN_F9R2 register *******************/
#define CAN_F9R2_FB0 0x00000001U /*!<Filter bit 0 */
#define CAN_F9R2_FB1 0x00000002U /*!<Filter bit 1 */
#define CAN_F9R2_FB2 0x00000004U /*!<Filter bit 2 */
#define CAN_F9R2_FB3 0x00000008U /*!<Filter bit 3 */
#define CAN_F9R2_FB4 0x00000010U /*!<Filter bit 4 */
#define CAN_F9R2_FB5 0x00000020U /*!<Filter bit 5 */
#define CAN_F9R2_FB6 0x00000040U /*!<Filter bit 6 */
#define CAN_F9R2_FB7 0x00000080U /*!<Filter bit 7 */
#define CAN_F9R2_FB8 0x00000100U /*!<Filter bit 8 */
#define CAN_F9R2_FB9 0x00000200U /*!<Filter bit 9 */
#define CAN_F9R2_FB10 0x00000400U /*!<Filter bit 10 */
#define CAN_F9R2_FB11 0x00000800U /*!<Filter bit 11 */
#define CAN_F9R2_FB12 0x00001000U /*!<Filter bit 12 */
#define CAN_F9R2_FB13 0x00002000U /*!<Filter bit 13 */
#define CAN_F9R2_FB14 0x00004000U /*!<Filter bit 14 */
#define CAN_F9R2_FB15 0x00008000U /*!<Filter bit 15 */
#define CAN_F9R2_FB16 0x00010000U /*!<Filter bit 16 */
#define CAN_F9R2_FB17 0x00020000U /*!<Filter bit 17 */
#define CAN_F9R2_FB18 0x00040000U /*!<Filter bit 18 */
#define CAN_F9R2_FB19 0x00080000U /*!<Filter bit 19 */
#define CAN_F9R2_FB20 0x00100000U /*!<Filter bit 20 */
#define CAN_F9R2_FB21 0x00200000U /*!<Filter bit 21 */
#define CAN_F9R2_FB22 0x00400000U /*!<Filter bit 22 */
#define CAN_F9R2_FB23 0x00800000U /*!<Filter bit 23 */
#define CAN_F9R2_FB24 0x01000000U /*!<Filter bit 24 */
#define CAN_F9R2_FB25 0x02000000U /*!<Filter bit 25 */
#define CAN_F9R2_FB26 0x04000000U /*!<Filter bit 26 */
#define CAN_F9R2_FB27 0x08000000U /*!<Filter bit 27 */
#define CAN_F9R2_FB28 0x10000000U /*!<Filter bit 28 */
#define CAN_F9R2_FB29 0x20000000U /*!<Filter bit 29 */
#define CAN_F9R2_FB30 0x40000000U /*!<Filter bit 30 */
#define CAN_F9R2_FB31 0x80000000U /*!<Filter bit 31 */
/******************* Bit definition for CAN_F10R2 register ******************/
#define CAN_F10R2_FB0 0x00000001U /*!<Filter bit 0 */
#define CAN_F10R2_FB1 0x00000002U /*!<Filter bit 1 */
#define CAN_F10R2_FB2 0x00000004U /*!<Filter bit 2 */
#define CAN_F10R2_FB3 0x00000008U /*!<Filter bit 3 */
#define CAN_F10R2_FB4 0x00000010U /*!<Filter bit 4 */
#define CAN_F10R2_FB5 0x00000020U /*!<Filter bit 5 */
#define CAN_F10R2_FB6 0x00000040U /*!<Filter bit 6 */
#define CAN_F10R2_FB7 0x00000080U /*!<Filter bit 7 */
#define CAN_F10R2_FB8 0x00000100U /*!<Filter bit 8 */
#define CAN_F10R2_FB9 0x00000200U /*!<Filter bit 9 */
#define CAN_F10R2_FB10 0x00000400U /*!<Filter bit 10 */
#define CAN_F10R2_FB11 0x00000800U /*!<Filter bit 11 */
#define CAN_F10R2_FB12 0x00001000U /*!<Filter bit 12 */
#define CAN_F10R2_FB13 0x00002000U /*!<Filter bit 13 */
#define CAN_F10R2_FB14 0x00004000U /*!<Filter bit 14 */
#define CAN_F10R2_FB15 0x00008000U /*!<Filter bit 15 */
#define CAN_F10R2_FB16 0x00010000U /*!<Filter bit 16 */
#define CAN_F10R2_FB17 0x00020000U /*!<Filter bit 17 */
#define CAN_F10R2_FB18 0x00040000U /*!<Filter bit 18 */
#define CAN_F10R2_FB19 0x00080000U /*!<Filter bit 19 */
#define CAN_F10R2_FB20 0x00100000U /*!<Filter bit 20 */
#define CAN_F10R2_FB21 0x00200000U /*!<Filter bit 21 */
#define CAN_F10R2_FB22 0x00400000U /*!<Filter bit 22 */
#define CAN_F10R2_FB23 0x00800000U /*!<Filter bit 23 */
#define CAN_F10R2_FB24 0x01000000U /*!<Filter bit 24 */
#define CAN_F10R2_FB25 0x02000000U /*!<Filter bit 25 */
#define CAN_F10R2_FB26 0x04000000U /*!<Filter bit 26 */
#define CAN_F10R2_FB27 0x08000000U /*!<Filter bit 27 */
#define CAN_F10R2_FB28 0x10000000U /*!<Filter bit 28 */
#define CAN_F10R2_FB29 0x20000000U /*!<Filter bit 29 */
#define CAN_F10R2_FB30 0x40000000U /*!<Filter bit 30 */
#define CAN_F10R2_FB31 0x80000000U /*!<Filter bit 31 */
/******************* Bit definition for CAN_F11R2 register ******************/
#define CAN_F11R2_FB0 0x00000001U /*!<Filter bit 0 */
#define CAN_F11R2_FB1 0x00000002U /*!<Filter bit 1 */
#define CAN_F11R2_FB2 0x00000004U /*!<Filter bit 2 */
#define CAN_F11R2_FB3 0x00000008U /*!<Filter bit 3 */
#define CAN_F11R2_FB4 0x00000010U /*!<Filter bit 4 */
#define CAN_F11R2_FB5 0x00000020U /*!<Filter bit 5 */
#define CAN_F11R2_FB6 0x00000040U /*!<Filter bit 6 */
#define CAN_F11R2_FB7 0x00000080U /*!<Filter bit 7 */
#define CAN_F11R2_FB8 0x00000100U /*!<Filter bit 8 */
#define CAN_F11R2_FB9 0x00000200U /*!<Filter bit 9 */
#define CAN_F11R2_FB10 0x00000400U /*!<Filter bit 10 */
#define CAN_F11R2_FB11 0x00000800U /*!<Filter bit 11 */
#define CAN_F11R2_FB12 0x00001000U /*!<Filter bit 12 */
#define CAN_F11R2_FB13 0x00002000U /*!<Filter bit 13 */
#define CAN_F11R2_FB14 0x00004000U /*!<Filter bit 14 */
#define CAN_F11R2_FB15 0x00008000U /*!<Filter bit 15 */
#define CAN_F11R2_FB16 0x00010000U /*!<Filter bit 16 */
#define CAN_F11R2_FB17 0x00020000U /*!<Filter bit 17 */
#define CAN_F11R2_FB18 0x00040000U /*!<Filter bit 18 */
#define CAN_F11R2_FB19 0x00080000U /*!<Filter bit 19 */
#define CAN_F11R2_FB20 0x00100000U /*!<Filter bit 20 */
#define CAN_F11R2_FB21 0x00200000U /*!<Filter bit 21 */
#define CAN_F11R2_FB22 0x00400000U /*!<Filter bit 22 */
#define CAN_F11R2_FB23 0x00800000U /*!<Filter bit 23 */
#define CAN_F11R2_FB24 0x01000000U /*!<Filter bit 24 */
#define CAN_F11R2_FB25 0x02000000U /*!<Filter bit 25 */
#define CAN_F11R2_FB26 0x04000000U /*!<Filter bit 26 */
#define CAN_F11R2_FB27 0x08000000U /*!<Filter bit 27 */
#define CAN_F11R2_FB28 0x10000000U /*!<Filter bit 28 */
#define CAN_F11R2_FB29 0x20000000U /*!<Filter bit 29 */
#define CAN_F11R2_FB30 0x40000000U /*!<Filter bit 30 */
#define CAN_F11R2_FB31 0x80000000U /*!<Filter bit 31 */
/******************* Bit definition for CAN_F12R2 register ******************/
#define CAN_F12R2_FB0 0x00000001U /*!<Filter bit 0 */
#define CAN_F12R2_FB1 0x00000002U /*!<Filter bit 1 */
#define CAN_F12R2_FB2 0x00000004U /*!<Filter bit 2 */
#define CAN_F12R2_FB3 0x00000008U /*!<Filter bit 3 */
#define CAN_F12R2_FB4 0x00000010U /*!<Filter bit 4 */
#define CAN_F12R2_FB5 0x00000020U /*!<Filter bit 5 */
#define CAN_F12R2_FB6 0x00000040U /*!<Filter bit 6 */
#define CAN_F12R2_FB7 0x00000080U /*!<Filter bit 7 */
#define CAN_F12R2_FB8 0x00000100U /*!<Filter bit 8 */
#define CAN_F12R2_FB9 0x00000200U /*!<Filter bit 9 */
#define CAN_F12R2_FB10 0x00000400U /*!<Filter bit 10 */
#define CAN_F12R2_FB11 0x00000800U /*!<Filter bit 11 */
#define CAN_F12R2_FB12 0x00001000U /*!<Filter bit 12 */
#define CAN_F12R2_FB13 0x00002000U /*!<Filter bit 13 */
#define CAN_F12R2_FB14 0x00004000U /*!<Filter bit 14 */
#define CAN_F12R2_FB15 0x00008000U /*!<Filter bit 15 */
#define CAN_F12R2_FB16 0x00010000U /*!<Filter bit 16 */
#define CAN_F12R2_FB17 0x00020000U /*!<Filter bit 17 */
#define CAN_F12R2_FB18 0x00040000U /*!<Filter bit 18 */
#define CAN_F12R2_FB19 0x00080000U /*!<Filter bit 19 */
#define CAN_F12R2_FB20 0x00100000U /*!<Filter bit 20 */
#define CAN_F12R2_FB21 0x00200000U /*!<Filter bit 21 */
#define CAN_F12R2_FB22 0x00400000U /*!<Filter bit 22 */
#define CAN_F12R2_FB23 0x00800000U /*!<Filter bit 23 */
#define CAN_F12R2_FB24 0x01000000U /*!<Filter bit 24 */
#define CAN_F12R2_FB25 0x02000000U /*!<Filter bit 25 */
#define CAN_F12R2_FB26 0x04000000U /*!<Filter bit 26 */
#define CAN_F12R2_FB27 0x08000000U /*!<Filter bit 27 */
#define CAN_F12R2_FB28 0x10000000U /*!<Filter bit 28 */
#define CAN_F12R2_FB29 0x20000000U /*!<Filter bit 29 */
#define CAN_F12R2_FB30 0x40000000U /*!<Filter bit 30 */
#define CAN_F12R2_FB31 0x80000000U /*!<Filter bit 31 */
/******************* Bit definition for CAN_F13R2 register ******************/
#define CAN_F13R2_FB0 0x00000001U /*!<Filter bit 0 */
#define CAN_F13R2_FB1 0x00000002U /*!<Filter bit 1 */
#define CAN_F13R2_FB2 0x00000004U /*!<Filter bit 2 */
#define CAN_F13R2_FB3 0x00000008U /*!<Filter bit 3 */
#define CAN_F13R2_FB4 0x00000010U /*!<Filter bit 4 */
#define CAN_F13R2_FB5 0x00000020U /*!<Filter bit 5 */
#define CAN_F13R2_FB6 0x00000040U /*!<Filter bit 6 */
#define CAN_F13R2_FB7 0x00000080U /*!<Filter bit 7 */
#define CAN_F13R2_FB8 0x00000100U /*!<Filter bit 8 */
#define CAN_F13R2_FB9 0x00000200U /*!<Filter bit 9 */
#define CAN_F13R2_FB10 0x00000400U /*!<Filter bit 10 */
#define CAN_F13R2_FB11 0x00000800U /*!<Filter bit 11 */
#define CAN_F13R2_FB12 0x00001000U /*!<Filter bit 12 */
#define CAN_F13R2_FB13 0x00002000U /*!<Filter bit 13 */
#define CAN_F13R2_FB14 0x00004000U /*!<Filter bit 14 */
#define CAN_F13R2_FB15 0x00008000U /*!<Filter bit 15 */
#define CAN_F13R2_FB16 0x00010000U /*!<Filter bit 16 */
#define CAN_F13R2_FB17 0x00020000U /*!<Filter bit 17 */
#define CAN_F13R2_FB18 0x00040000U /*!<Filter bit 18 */
#define CAN_F13R2_FB19 0x00080000U /*!<Filter bit 19 */
#define CAN_F13R2_FB20 0x00100000U /*!<Filter bit 20 */
#define CAN_F13R2_FB21 0x00200000U /*!<Filter bit 21 */
#define CAN_F13R2_FB22 0x00400000U /*!<Filter bit 22 */
#define CAN_F13R2_FB23 0x00800000U /*!<Filter bit 23 */
#define CAN_F13R2_FB24 0x01000000U /*!<Filter bit 24 */
#define CAN_F13R2_FB25 0x02000000U /*!<Filter bit 25 */
#define CAN_F13R2_FB26 0x04000000U /*!<Filter bit 26 */
#define CAN_F13R2_FB27 0x08000000U /*!<Filter bit 27 */
#define CAN_F13R2_FB28 0x10000000U /*!<Filter bit 28 */
#define CAN_F13R2_FB29 0x20000000U /*!<Filter bit 29 */
#define CAN_F13R2_FB30 0x40000000U /*!<Filter bit 30 */
#define CAN_F13R2_FB31 0x80000000U /*!<Filter bit 31 */
/******************************************************************************/
/* */
/* HDMI-CEC (CEC) */
/* */
/******************************************************************************/
/******************* Bit definition for CEC_CR register *********************/
#define CEC_CR_CECEN 0x00000001U /*!< CEC Enable */
#define CEC_CR_TXSOM 0x00000002U /*!< CEC Tx Start Of Message */
#define CEC_CR_TXEOM 0x00000004U /*!< CEC Tx End Of Message */
/******************* Bit definition for CEC_CFGR register *******************/
#define CEC_CFGR_SFT 0x00000007U /*!< CEC Signal Free Time */
#define CEC_CFGR_RXTOL 0x00000008U /*!< CEC Tolerance */
#define CEC_CFGR_BRESTP 0x00000010U /*!< CEC Rx Stop */
#define CEC_CFGR_BREGEN 0x00000020U /*!< CEC Bit Rising Error generation */
#define CEC_CFGR_LBPEGEN 0x00000040U /*!< CEC Long Period Error generation */
#define CEC_CFGR_BRDNOGEN 0x00000080U /*!< CEC Broadcast no Error generation */
#define CEC_CFGR_SFTOPT 0x00000100U /*!< CEC Signal Free Time optional */
#define CEC_CFGR_OAR 0x7FFF0000U /*!< CEC Own Address */
#define CEC_CFGR_LSTN 0x80000000U /*!< CEC Listen mode */
/******************* Bit definition for CEC_TXDR register *******************/
#define CEC_TXDR_TXD 0x000000FFU /*!< CEC Tx Data */
/******************* Bit definition for CEC_RXDR register *******************/
#define CEC_TXDR_RXD 0x000000FFU /*!< CEC Rx Data */
/******************* Bit definition for CEC_ISR register ********************/
#define CEC_ISR_RXBR 0x00000001U /*!< CEC Rx-Byte Received */
#define CEC_ISR_RXEND 0x00000002U /*!< CEC End Of Reception */
#define CEC_ISR_RXOVR 0x00000004U /*!< CEC Rx-Overrun */
#define CEC_ISR_BRE 0x00000008U /*!< CEC Rx Bit Rising Error */
#define CEC_ISR_SBPE 0x00000010U /*!< CEC Rx Short Bit period Error */
#define CEC_ISR_LBPE 0x00000020U /*!< CEC Rx Long Bit period Error */
#define CEC_ISR_RXACKE 0x00000040U /*!< CEC Rx Missing Acknowledge */
#define CEC_ISR_ARBLST 0x00000080U /*!< CEC Arbitration Lost */
#define CEC_ISR_TXBR 0x00000100U /*!< CEC Tx Byte Request */
#define CEC_ISR_TXEND 0x00000200U /*!< CEC End of Transmission */
#define CEC_ISR_TXUDR 0x00000400U /*!< CEC Tx-Buffer Underrun */
#define CEC_ISR_TXERR 0x00000800U /*!< CEC Tx-Error */
#define CEC_ISR_TXACKE 0x00001000U /*!< CEC Tx Missing Acknowledge */
/******************* Bit definition for CEC_IER register ********************/
#define CEC_IER_RXBRIE 0x00000001U /*!< CEC Rx-Byte Received IT Enable */
#define CEC_IER_RXENDIE 0x00000002U /*!< CEC End Of Reception IT Enable */
#define CEC_IER_RXOVRIE 0x00000004U /*!< CEC Rx-Overrun IT Enable */
#define CEC_IER_BREIE 0x00000008U /*!< CEC Rx Bit Rising Error IT Enable */
#define CEC_IER_SBPEIE 0x00000010U /*!< CEC Rx Short Bit period Error IT Enable*/
#define CEC_IER_LBPEIE 0x00000020U /*!< CEC Rx Long Bit period Error IT Enable */
#define CEC_IER_RXACKEIE 0x00000040U /*!< CEC Rx Missing Acknowledge IT Enable */
#define CEC_IER_ARBLSTIE 0x00000080U /*!< CEC Arbitration Lost IT Enable */
#define CEC_IER_TXBRIE 0x00000100U /*!< CEC Tx Byte Request IT Enable */
#define CEC_IER_TXENDIE 0x00000200U /*!< CEC End of Transmission IT Enable */
#define CEC_IER_TXUDRIE 0x00000400U /*!< CEC Tx-Buffer Underrun IT Enable */
#define CEC_IER_TXERRIE 0x00000800U /*!< CEC Tx-Error IT Enable */
#define CEC_IER_TXACKEIE 0x00001000U /*!< CEC Tx Missing Acknowledge IT Enable */
/******************************************************************************/
/* */
/* CRC calculation unit */
/* */
/******************************************************************************/
/******************* Bit definition for CRC_DR register *********************/
#define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR 0x000000FFU /*!< General-purpose 8-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET 0x00000001U /*!< RESET the CRC computation unit bit */
#define CRC_CR_POLYSIZE 0x00000018U /*!< Polynomial size bits */
#define CRC_CR_POLYSIZE_0 0x00000008U /*!< Polynomial size bit 0 */
#define CRC_CR_POLYSIZE_1 0x00000010U /*!< Polynomial size bit 1 */
#define CRC_CR_REV_IN 0x00000060U /*!< REV_IN Reverse Input Data bits */
#define CRC_CR_REV_IN_0 0x00000020U /*!< Bit 0 */
#define CRC_CR_REV_IN_1 0x00000040U /*!< Bit 1 */
#define CRC_CR_REV_OUT 0x00000080U /*!< REV_OUT Reverse Output Data bits */
/******************* Bit definition for CRC_INIT register *******************/
#define CRC_INIT_INIT 0xFFFFFFFFU /*!< Initial CRC value bits */
/******************* Bit definition for CRC_POL register ********************/
#define CRC_POL_POL 0xFFFFFFFFU /*!< Coefficients of the polynomial */
/******************************************************************************/
/* */
/* Digital to Analog Converter */
/* */
/******************************************************************************/
/******************** Bit definition for DAC_CR register ********************/
#define DAC_CR_EN1 0x00000001U /*!<DAC channel1 enable */
#define DAC_CR_BOFF1 0x00000002U /*!<DAC channel1 output buffer disable */
#define DAC_CR_TEN1 0x00000004U /*!<DAC channel1 Trigger enable */
#define DAC_CR_TSEL1 0x00000038U /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
#define DAC_CR_TSEL1_0 0x00000008U /*!<Bit 0 */
#define DAC_CR_TSEL1_1 0x00000010U /*!<Bit 1 */
#define DAC_CR_TSEL1_2 0x00000020U /*!<Bit 2 */
#define DAC_CR_WAVE1 0x000000C0U /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enablEU) */
#define DAC_CR_WAVE1_0 0x00000040U /*!<Bit 0 */
#define DAC_CR_WAVE1_1 0x00000080U /*!<Bit 1 */
#define DAC_CR_MAMP1 0x00000F00U /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
#define DAC_CR_MAMP1_0 0x00000100U /*!<Bit 0 */
#define DAC_CR_MAMP1_1 0x00000200U /*!<Bit 1 */
#define DAC_CR_MAMP1_2 0x00000400U /*!<Bit 2 */
#define DAC_CR_MAMP1_3 0x00000800U /*!<Bit 3 */
#define DAC_CR_DMAEN1 0x00001000U /*!<DAC channel1 DMA enable */
#define DAC_CR_DMAUDRIE1 0x00002000U /*!<DAC channel1 DMA underrun interrupt enable */
#define DAC_CR_EN2 0x00010000U /*!<DAC channel2 enable */
#define DAC_CR_BOFF2 0x00020000U /*!<DAC channel2 output buffer disable */
#define DAC_CR_TEN2 0x00040000U /*!<DAC channel2 Trigger enable */
#define DAC_CR_TSEL2 0x00380000U /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
#define DAC_CR_TSEL2_0 0x00080000U /*!<Bit 0 */
#define DAC_CR_TSEL2_1 0x00100000U /*!<Bit 1 */
#define DAC_CR_TSEL2_2 0x00200000U /*!<Bit 2 */
#define DAC_CR_WAVE2 0x00C00000U /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
#define DAC_CR_WAVE2_0 0x00400000U /*!<Bit 0 */
#define DAC_CR_WAVE2_1 0x00800000U /*!<Bit 1 */
#define DAC_CR_MAMP2 0x0F000000U /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
#define DAC_CR_MAMP2_0 0x01000000U /*!<Bit 0 */
#define DAC_CR_MAMP2_1 0x02000000U /*!<Bit 1 */
#define DAC_CR_MAMP2_2 0x04000000U /*!<Bit 2 */
#define DAC_CR_MAMP2_3 0x08000000U /*!<Bit 3 */
#define DAC_CR_DMAEN2 0x10000000U /*!<DAC channel2 DMA enable */
#define DAC_CR_DMAUDRIE2 0x20000000U /*!<DAC channel2 DMA underrun interrupt enable */
/***************** Bit definition for DAC_SWTRIGR register ******************/
#define DAC_SWTRIGR_SWTRIG1 0x01U /*!<DAC channel1 software trigger */
#define DAC_SWTRIGR_SWTRIG2 0x02U /*!<DAC channel2 software trigger */
/***************** Bit definition for DAC_DHR12R1 register ******************/
#define DAC_DHR12R1_DACC1DHR 0x0FFFU /*!<DAC channel1 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12L1 register ******************/
#define DAC_DHR12L1_DACC1DHR 0xFFF0U /*!<DAC channel1 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8R1 register ******************/
#define DAC_DHR8R1_DACC1DHR 0xFFU /*!<DAC channel1 8-bit Right aligned data */
/***************** Bit definition for DAC_DHR12R2 register ******************/
#define DAC_DHR12R2_DACC2DHR 0x0FFFU /*!<DAC channel2 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12L2 register ******************/
#define DAC_DHR12L2_DACC2DHR 0xFFF0U /*!<DAC channel2 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8R2 register ******************/
#define DAC_DHR8R2_DACC2DHR 0xFFU /*!<DAC channel2 8-bit Right aligned data */
/***************** Bit definition for DAC_DHR12RD register ******************/
#define DAC_DHR12RD_DACC1DHR 0x00000FFFU /*!<DAC channel1 12-bit Right aligned data */
#define DAC_DHR12RD_DACC2DHR 0x0FFF0000U /*!<DAC channel2 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12LD register ******************/
#define DAC_DHR12LD_DACC1DHR 0x0000FFF0U /*!<DAC channel1 12-bit Left aligned data */
#define DAC_DHR12LD_DACC2DHR 0xFFF00000U /*!<DAC channel2 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8RD register ******************/
#define DAC_DHR8RD_DACC1DHR 0x00FFU /*!<DAC channel1 8-bit Right aligned data */
#define DAC_DHR8RD_DACC2DHR 0xFF00U /*!<DAC channel2 8-bit Right aligned data */
/******************* Bit definition for DAC_DOR1 register *******************/
#define DAC_DOR1_DACC1DOR 0x0FFFU /*!<DAC channel1 data output */
/******************* Bit definition for DAC_DOR2 register *******************/
#define DAC_DOR2_DACC2DOR 0x0FFFU /*!<DAC channel2 data output */
/******************** Bit definition for DAC_SR register ********************/
#define DAC_SR_DMAUDR1 0x00002000U /*!<DAC channel1 DMA underrun flag */
#define DAC_SR_DMAUDR2 0x20000000U /*!<DAC channel2 DMA underrun flag */
/******************************************************************************/
/* */
/* Digital Filter for Sigma Delta Modulators */
/* */
/******************************************************************************/
/**************** DFSDM channel configuration registers ********************/
/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
#define DFSDM_CHCFGR1_DFSDMEN 0x80000000U /*!< Global enable for DFSDM interface */
#define DFSDM_CHCFGR1_CKOUTSRC 0x40000000U /*!< Output serial clock source selection */
#define DFSDM_CHCFGR1_CKOUTDIV 0x00FF0000U /*!< CKOUTDIV[7:0] output serial clock divider */
#define DFSDM_CHCFGR1_DATPACK 0x0000C000U /*!< DATPACK[1:0] Data packing mode */
#define DFSDM_CHCFGR1_DATPACK_1 0x00008000U /*!< Data packing mode, Bit 1 */
#define DFSDM_CHCFGR1_DATPACK_0 0x00004000U /*!< Data packing mode, Bit 0 */
#define DFSDM_CHCFGR1_DATMPX 0x00003000U /*!< DATMPX[1:0] Input data multiplexer for channel y */
#define DFSDM_CHCFGR1_DATMPX_1 0x00002000U /*!< Input data multiplexer for channel y, Bit 1 */
#define DFSDM_CHCFGR1_DATMPX_0 0x00001000U /*!< Input data multiplexer for channel y, Bit 0 */
#define DFSDM_CHCFGR1_CHINSEL 0x00000100U /*!< Serial inputs selection for channel y */
#define DFSDM_CHCFGR1_CHEN 0x00000080U /*!< Channel y enable */
#define DFSDM_CHCFGR1_CKABEN 0x00000040U /*!< Clock absence detector enable on channel y */
#define DFSDM_CHCFGR1_SCDEN 0x00000020U /*!< Short circuit detector enable on channel y */
#define DFSDM_CHCFGR1_SPICKSEL 0x0000000CU /*!< SPICKSEL[1:0] SPI clock select for channel y */
#define DFSDM_CHCFGR1_SPICKSEL_1 0x00000008U /*!< SPI clock select for channel y, Bit 1 */
#define DFSDM_CHCFGR1_SPICKSEL_0 0x00000004U /*!< SPI clock select for channel y, Bit 0 */
#define DFSDM_CHCFGR1_SITP 0x00000003U /*!< SITP[1:0] Serial interface type for channel y */
#define DFSDM_CHCFGR1_SITP_1 0x00000002U /*!< Serial interface type for channel y, Bit 1 */
#define DFSDM_CHCFGR1_SITP_0 0x00000001U /*!< Serial interface type for channel y, Bit 0 */
/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
#define DFSDM_CHCFGR2_OFFSET 0xFFFFFF00U /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
#define DFSDM_CHCFGR2_DTRBS 0x000000F8U /*!< DTRBS[4:0] Data right bit-shift for channel y */
/****************** Bit definition for DFSDM_CHAWSCDR register *****************/
#define DFSDM_CHAWSCDR_AWFORD 0x00C00000U /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
#define DFSDM_CHAWSCDR_AWFORD_1 0x00800000U /*!< Analog watchdog Sinc filter order on channel y, Bit 1 */
#define DFSDM_CHAWSCDR_AWFORD_0 0x00400000U /*!< Analog watchdog Sinc filter order on channel y, Bit 0 */
#define DFSDM_CHAWSCDR_AWFOSR 0x001F0000U /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
#define DFSDM_CHAWSCDR_BKSCD 0x0000F000U /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
#define DFSDM_CHAWSCDR_SCDT 0x000000FFU /*!< SCDT[7:0] Short circuit detector threshold for channel y */
/**************** Bit definition for DFSDM_CHWDATR register *******************/
#define DFSDM_CHWDATR_WDATA 0x0000FFFFU /*!< WDATA[15:0] Input channel y watchdog data */
/**************** Bit definition for DFSDM_CHDATINR register *****************/
#define DFSDM_CHDATINR_INDAT0 0x0000FFFFU /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
#define DFSDM_CHDATINR_INDAT1 0xFFFF0000U /*!< INDAT0[15:0] Input data for channel y */
/************************ DFSDM module registers ****************************/
/******************** Bit definition for DFSDM_FLTCR1 register *******************/
#define DFSDM_FLTCR1_AWFSEL 0x40000000U /*!< Analog watchdog fast mode select */
#define DFSDM_FLTCR1_FAST 0x20000000U /*!< Fast conversion mode selection */
#define DFSDM_FLTCR1_RCH 0x07000000U /*!< RCH[2:0] Regular channel selection */
#define DFSDM_FLTCR1_RDMAEN 0x00200000U /*!< DMA channel enabled to read data for the regular conversion */
#define DFSDM_FLTCR1_RSYNC 0x00080000U /*!< Launch regular conversion synchronously with DFSDMx */
#define DFSDM_FLTCR1_RCONT 0x00040000U /*!< Continuous mode selection for regular conversions */
#define DFSDM_FLTCR1_RSWSTART 0x00020000U /*!< Software start of a conversion on the regular channel */
#define DFSDM_FLTCR1_JEXTEN 0x00006000U /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
#define DFSDM_FLTCR1_JEXTEN_1 0x00004000U /*!< Trigger enable and trigger edge selection for injected conversions, Bit 1 */
#define DFSDM_FLTCR1_JEXTEN_0 0x00002000U /*!< Trigger enable and trigger edge selection for injected conversions, Bit 0 */
#define DFSDM_FLTCR1_JEXTSEL 0x00001F00U /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
#define DFSDM_FLTCR1_JEXTSEL_0 0x00000100U /*!< Trigger signal selection for launching injected conversions, Bit 0 */
#define DFSDM_FLTCR1_JEXTSEL_1 0x00000200U /*!< Trigger signal selection for launching injected conversions, Bit 1 */
#define DFSDM_FLTCR1_JEXTSEL_2 0x00000400U /*!< Trigger signal selection for launching injected conversions, Bit 2 */
#define DFSDM_FLTCR1_JEXTSEL_3 0x00000800U /*!< Trigger signal selection for launching injected conversions, Bit 3 */
#define DFSDM_FLTCR1_JEXTSEL_4 0x00001000U /*!< Trigger signal selection for launching injected conversions, Bit 4 */
#define DFSDM_FLTCR1_JDMAEN 0x00000020U /*!< DMA channel enabled to read data for the injected channel group */
#define DFSDM_FLTCR1_JSCAN 0x00000010U /*!< Scanning conversion in continuous mode selection for injected conversions */
#define DFSDM_FLTCR1_JSYNC 0x00000008U /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
#define DFSDM_FLTCR1_JSWSTART 0x00000002U /*!< Start the conversion of the injected group of channels */
#define DFSDM_FLTCR1_DFEN 0x00000001U /*!< DFSDM enable */
/******************** Bit definition for DFSDM_FLTCR2 register *******************/
#define DFSDM_FLTCR2_AWDCH 0x00FF0000U /*!< AWDCH[7:0] Analog watchdog channel selection */
#define DFSDM_FLTCR2_EXCH 0x0000FF00U /*!< EXCH[7:0] Extreme detector channel selection */
#define DFSDM_FLTCR2_CKABIE 0x00000040U /*!< Clock absence interrupt enable */
#define DFSDM_FLTCR2_SCDIE 0x00000020U /*!< Short circuit detector interrupt enable */
#define DFSDM_FLTCR2_AWDIE 0x00000010U /*!< Analog watchdog interrupt enable */
#define DFSDM_FLTCR2_ROVRIE 0x00000008U /*!< Regular data overrun interrupt enable */
#define DFSDM_FLTCR2_JOVRIE 0x00000004U /*!< Injected data overrun interrupt enable */
#define DFSDM_FLTCR2_REOCIE 0x00000002U /*!< Regular end of conversion interrupt enable */
#define DFSDM_FLTCR2_JEOCIE 0x00000001U /*!< Injected end of conversion interrupt enable */
/******************** Bit definition for DFSDM_FLTISR register *******************/
#define DFSDM_FLTISR_SCDF 0xFF000000U /*!< SCDF[7:0] Short circuit detector flag */
#define DFSDM_FLTISR_CKABF 0x00FF0000U /*!< CKABF[7:0] Clock absence flag */
#define DFSDM_FLTISR_RCIP 0x00004000U /*!< Regular conversion in progress status */
#define DFSDM_FLTISR_JCIP 0x00002000U /*!< Injected conversion in progress status */
#define DFSDM_FLTISR_AWDF 0x00000010U /*!< Analog watchdog */
#define DFSDM_FLTISR_ROVRF 0x00000008U /*!< Regular conversion overrun flag */
#define DFSDM_FLTISR_JOVRF 0x00000004U /*!< Injected conversion overrun flag */
#define DFSDM_FLTISR_REOCF 0x00000002U /*!< End of regular conversion flag */
#define DFSDM_FLTISR_JEOCF 0x00000001U /*!< End of injected conversion flag */
/******************** Bit definition for DFSDM_FLTICR register *******************/
#define DFSDM_FLTICR_CLRSCSDF 0xFF000000U /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
#define DFSDM_FLTICR_CLRCKABF 0x00FF0000U /*!< CLRCKABF[7:0] Clear the clock absence flag */
#define DFSDM_FLTICR_CLRROVRF 0x00000008U /*!< Clear the regular conversion overrun flag */
#define DFSDM_FLTICR_CLRJOVRF 0x00000004U /*!< Clear the injected conversion overrun flag */
/******************* Bit definition for DFSDM_FLTJCHGR register ******************/
#define DFSDM_FLTJCHGR_JCHG 0x000000FFU /*!< JCHG[7:0] Injected channel group selection */
/******************** Bit definition for DFSDM_FLTFCR register *******************/
#define DFSDM_FLTFCR_FORD 0xE0000000U /*!< FORD[2:0] Sinc filter order */
#define DFSDM_FLTFCR_FORD_2 0x80000000U /*!< Sinc filter order, Bit 2 */
#define DFSDM_FLTFCR_FORD_1 0x40000000U /*!< Sinc filter order, Bit 1 */
#define DFSDM_FLTFCR_FORD_0 0x20000000U /*!< Sinc filter order, Bit 0 */
#define DFSDM_FLTFCR_FOSR 0x03FF0000U /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
#define DFSDM_FLTFCR_IOSR 0x000000FFU /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
/****************** Bit definition for DFSDM_FLTJDATAR register *****************/
#define DFSDM_FLTJDATAR_JDATA 0xFFFFFF00U /*!< JDATA[23:0] Injected group conversion data */
#define DFSDM_FLTJDATAR_JDATACH 0x00000007U /*!< JDATACH[2:0] Injected channel most recently converted */
/****************** Bit definition for DFSDM_FLTRDATAR register *****************/
#define DFSDM_FLTRDATAR_RDATA 0xFFFFFF00U /*!< RDATA[23:0] Regular channel conversion data */
#define DFSDM_FLTRDATAR_RPEND 0x00000010U /*!< RPEND Regular channel pending data */
#define DFSDM_FLTRDATAR_RDATACH 0x00000007U /*!< RDATACH[2:0] Regular channel most recently converted */
/****************** Bit definition for DFSDM_FLTAWHTR register ******************/
#define DFSDM_FLTAWHTR_AWHT 0xFFFFFF00U /*!< AWHT[23:0] Analog watchdog high threshold */
#define DFSDM_FLTAWHTR_BKAWH 0x0000000FU /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
/****************** Bit definition for DFSDM_FLTAWLTR register ******************/
#define DFSDM_FLTAWLTR_AWLT 0xFFFFFF00U /*!< AWLT[23:0] Analog watchdog low threshold */
#define DFSDM_FLTAWLTR_BKAWL 0x0000000FU /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
/****************** Bit definition for DFSDM_FLTAWSR register ******************/
#define DFSDM_FLTAWSR_AWHTF 0x0000FF00U /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
#define DFSDM_FLTAWSR_AWLTF 0x000000FFU /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
/****************** Bit definition for DFSDM_FLTAWCFR register *****************/
#define DFSDM_FLTAWCFR_CLRAWHTF 0x0000FF00U /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
#define DFSDM_FLTAWCFR_CLRAWLTF 0x000000FFU /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
/****************** Bit definition for DFSDM_FLTEXMAX register ******************/
#define DFSDM_FLTEXMAX_EXMAX 0xFFFFFF00U /*!< EXMAX[23:0] Extreme detector maximum value */
#define DFSDM_FLTEXMAX_EXMAXCH 0x00000007U /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
/****************** Bit definition for DFSDM_FLTEXMIN register ******************/
#define DFSDM_FLTEXMIN_EXMIN 0xFFFFFF00U /*!< EXMIN[23:0] Extreme detector minimum value */
#define DFSDM_FLTEXMIN_EXMINCH 0x00000007U /*!< EXMINCH[2:0] Extreme detector minimum data channel */
/****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
#define DFSDM_FLTCNVTIMR_CNVCNT 0xFFFFFFF0U /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
/******************************************************************************/
/* */
/* Debug MCU */
/* */
/******************************************************************************/
/******************************************************************************/
/* */
/* DCMI */
/* */
/******************************************************************************/
/******************** Bits definition for DCMI_CR register ******************/
#define DCMI_CR_CAPTURE 0x00000001U
#define DCMI_CR_CM 0x00000002U
#define DCMI_CR_CROP 0x00000004U
#define DCMI_CR_JPEG 0x00000008U
#define DCMI_CR_ESS 0x00000010U
#define DCMI_CR_PCKPOL 0x00000020U
#define DCMI_CR_HSPOL 0x00000040U
#define DCMI_CR_VSPOL 0x00000080U
#define DCMI_CR_FCRC_0 0x00000100U
#define DCMI_CR_FCRC_1 0x00000200U
#define DCMI_CR_EDM_0 0x00000400U
#define DCMI_CR_EDM_1 0x00000800U
#define DCMI_CR_CRE 0x00001000U
#define DCMI_CR_ENABLE 0x00004000U
#define DCMI_CR_BSM 0x00030000U
#define DCMI_CR_BSM_0 0x00010000U
#define DCMI_CR_BSM_1 0x00020000U
#define DCMI_CR_OEBS 0x00040000U
#define DCMI_CR_LSM 0x00080000U
#define DCMI_CR_OELS 0x00100000U
/******************** Bits definition for DCMI_SR register ******************/
#define DCMI_SR_HSYNC 0x00000001U
#define DCMI_SR_VSYNC 0x00000002U
#define DCMI_SR_FNE 0x00000004U
/******************** Bits definition for DCMI_RIS register ****************/
#define DCMI_RIS_FRAME_RIS 0x00000001U
#define DCMI_RIS_OVR_RIS 0x00000002U
#define DCMI_RIS_ERR_RIS 0x00000004U
#define DCMI_RIS_VSYNC_RIS 0x00000008U
#define DCMI_RIS_LINE_RIS 0x00000010U
/* Legacy defines */
#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
/******************** Bits definition for DCMI_IER register *****************/
#define DCMI_IER_FRAME_IE 0x00000001U
#define DCMI_IER_OVR_IE 0x00000002U
#define DCMI_IER_ERR_IE 0x00000004U
#define DCMI_IER_VSYNC_IE 0x00000008U
#define DCMI_IER_LINE_IE 0x00000010U
/******************** Bits definition for DCMI_MIS register *****************/
#define DCMI_MIS_FRAME_MIS 0x00000001U
#define DCMI_MIS_OVR_MIS 0x00000002U
#define DCMI_MIS_ERR_MIS 0x00000004U
#define DCMI_MIS_VSYNC_MIS 0x00000008U
#define DCMI_MIS_LINE_MIS 0x00000010U
/******************** Bits definition for DCMI_ICR register *****************/
#define DCMI_ICR_FRAME_ISC 0x00000001U
#define DCMI_ICR_OVR_ISC 0x00000002U
#define DCMI_ICR_ERR_ISC 0x00000004U
#define DCMI_ICR_VSYNC_ISC 0x00000008U
#define DCMI_ICR_LINE_ISC 0x00000010U
/******************** Bits definition for DCMI_ESCR register ******************/
#define DCMI_ESCR_FSC 0x000000FFU
#define DCMI_ESCR_LSC 0x0000FF00U
#define DCMI_ESCR_LEC 0x00FF0000U
#define DCMI_ESCR_FEC 0xFF000000U
/******************** Bits definition for DCMI_ESUR register ******************/
#define DCMI_ESUR_FSU 0x000000FFU
#define DCMI_ESUR_LSU 0x0000FF00U
#define DCMI_ESUR_LEU 0x00FF0000U
#define DCMI_ESUR_FEU 0xFF000000U
/******************** Bits definition for DCMI_CWSTRT register ******************/
#define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
#define DCMI_CWSTRT_VST 0x1FFF0000U
/******************** Bits definition for DCMI_CWSIZE register ******************/
#define DCMI_CWSIZE_CAPCNT 0x00003FFFU
#define DCMI_CWSIZE_VLINE 0x3FFF0000U
/******************** Bits definition for DCMI_DR register ******************/
#define DCMI_DR_BYTE0 0x000000FFU
#define DCMI_DR_BYTE1 0x0000FF00U
#define DCMI_DR_BYTE2 0x00FF0000U
#define DCMI_DR_BYTE3 0xFF000000U
/******************************************************************************/
/* */
/* DMA Controller */
/* */
/******************************************************************************/
/******************** Bits definition for DMA_SxCR register *****************/
#define DMA_SxCR_CHSEL 0x1E000000U
#define DMA_SxCR_CHSEL_0 0x02000000U
#define DMA_SxCR_CHSEL_1 0x04000000U
#define DMA_SxCR_CHSEL_2 0x08000000U
#define DMA_SxCR_CHSEL_3 0x10000000U
#define DMA_SxCR_MBURST 0x01800000U
#define DMA_SxCR_MBURST_0 0x00800000U
#define DMA_SxCR_MBURST_1 0x01000000U
#define DMA_SxCR_PBURST 0x00600000U
#define DMA_SxCR_PBURST_0 0x00200000U
#define DMA_SxCR_PBURST_1 0x00400000U
#define DMA_SxCR_CT 0x00080000U
#define DMA_SxCR_DBM 0x00040000U
#define DMA_SxCR_PL 0x00030000U
#define DMA_SxCR_PL_0 0x00010000U
#define DMA_SxCR_PL_1 0x00020000U
#define DMA_SxCR_PINCOS 0x00008000U
#define DMA_SxCR_MSIZE 0x00006000U
#define DMA_SxCR_MSIZE_0 0x00002000U
#define DMA_SxCR_MSIZE_1 0x00004000U
#define DMA_SxCR_PSIZE 0x00001800U
#define DMA_SxCR_PSIZE_0 0x00000800U
#define DMA_SxCR_PSIZE_1 0x00001000U
#define DMA_SxCR_MINC 0x00000400U
#define DMA_SxCR_PINC 0x00000200U
#define DMA_SxCR_CIRC 0x00000100U
#define DMA_SxCR_DIR 0x000000C0U
#define DMA_SxCR_DIR_0 0x00000040U
#define DMA_SxCR_DIR_1 0x00000080U
#define DMA_SxCR_PFCTRL 0x00000020U
#define DMA_SxCR_TCIE 0x00000010U
#define DMA_SxCR_HTIE 0x00000008U
#define DMA_SxCR_TEIE 0x00000004U
#define DMA_SxCR_DMEIE 0x00000002U
#define DMA_SxCR_EN 0x00000001U
/******************** Bits definition for DMA_SxCNDTR register **************/
#define DMA_SxNDT 0x0000FFFFU
#define DMA_SxNDT_0 0x00000001U
#define DMA_SxNDT_1 0x00000002U
#define DMA_SxNDT_2 0x00000004U
#define DMA_SxNDT_3 0x00000008U
#define DMA_SxNDT_4 0x00000010U
#define DMA_SxNDT_5 0x00000020U
#define DMA_SxNDT_6 0x00000040U
#define DMA_SxNDT_7 0x00000080U
#define DMA_SxNDT_8 0x00000100U
#define DMA_SxNDT_9 0x00000200U
#define DMA_SxNDT_10 0x00000400U
#define DMA_SxNDT_11 0x00000800U
#define DMA_SxNDT_12 0x00001000U
#define DMA_SxNDT_13 0x00002000U
#define DMA_SxNDT_14 0x00004000U
#define DMA_SxNDT_15 0x00008000U
/******************** Bits definition for DMA_SxFCR register ****************/
#define DMA_SxFCR_FEIE 0x00000080U
#define DMA_SxFCR_FS 0x00000038U
#define DMA_SxFCR_FS_0 0x00000008U
#define DMA_SxFCR_FS_1 0x00000010U
#define DMA_SxFCR_FS_2 0x00000020U
#define DMA_SxFCR_DMDIS 0x00000004U
#define DMA_SxFCR_FTH 0x00000003U
#define DMA_SxFCR_FTH_0 0x00000001U
#define DMA_SxFCR_FTH_1 0x00000002U
/******************** Bits definition for DMA_LISR register *****************/
#define DMA_LISR_TCIF3 0x08000000U
#define DMA_LISR_HTIF3 0x04000000U
#define DMA_LISR_TEIF3 0x02000000U
#define DMA_LISR_DMEIF3 0x01000000U
#define DMA_LISR_FEIF3 0x00400000U
#define DMA_LISR_TCIF2 0x00200000U
#define DMA_LISR_HTIF2 0x00100000U
#define DMA_LISR_TEIF2 0x00080000U
#define DMA_LISR_DMEIF2 0x00040000U
#define DMA_LISR_FEIF2 0x00010000U
#define DMA_LISR_TCIF1 0x00000800U
#define DMA_LISR_HTIF1 0x00000400U
#define DMA_LISR_TEIF1 0x00000200U
#define DMA_LISR_DMEIF1 0x00000100U
#define DMA_LISR_FEIF1 0x00000040U
#define DMA_LISR_TCIF0 0x00000020U
#define DMA_LISR_HTIF0 0x00000010U
#define DMA_LISR_TEIF0 0x00000008U
#define DMA_LISR_DMEIF0 0x00000004U
#define DMA_LISR_FEIF0 0x00000001U
/******************** Bits definition for DMA_HISR register *****************/
#define DMA_HISR_TCIF7 0x08000000U
#define DMA_HISR_HTIF7 0x04000000U
#define DMA_HISR_TEIF7 0x02000000U
#define DMA_HISR_DMEIF7 0x01000000U
#define DMA_HISR_FEIF7 0x00400000U
#define DMA_HISR_TCIF6 0x00200000U
#define DMA_HISR_HTIF6 0x00100000U
#define DMA_HISR_TEIF6 0x00080000U
#define DMA_HISR_DMEIF6 0x00040000U
#define DMA_HISR_FEIF6 0x00010000U
#define DMA_HISR_TCIF5 0x00000800U
#define DMA_HISR_HTIF5 0x00000400U
#define DMA_HISR_TEIF5 0x00000200U
#define DMA_HISR_DMEIF5 0x00000100U
#define DMA_HISR_FEIF5 0x00000040U
#define DMA_HISR_TCIF4 0x00000020U
#define DMA_HISR_HTIF4 0x00000010U
#define DMA_HISR_TEIF4 0x00000008U
#define DMA_HISR_DMEIF4 0x00000004U
#define DMA_HISR_FEIF4 0x00000001U
/******************** Bits definition for DMA_LIFCR register ****************/
#define DMA_LIFCR_CTCIF3 0x08000000U
#define DMA_LIFCR_CHTIF3 0x04000000U
#define DMA_LIFCR_CTEIF3 0x02000000U
#define DMA_LIFCR_CDMEIF3 0x01000000U
#define DMA_LIFCR_CFEIF3 0x00400000U
#define DMA_LIFCR_CTCIF2 0x00200000U
#define DMA_LIFCR_CHTIF2 0x00100000U
#define DMA_LIFCR_CTEIF2 0x00080000U
#define DMA_LIFCR_CDMEIF2 0x00040000U
#define DMA_LIFCR_CFEIF2 0x00010000U
#define DMA_LIFCR_CTCIF1 0x00000800U
#define DMA_LIFCR_CHTIF1 0x00000400U
#define DMA_LIFCR_CTEIF1 0x00000200U
#define DMA_LIFCR_CDMEIF1 0x00000100U
#define DMA_LIFCR_CFEIF1 0x00000040U
#define DMA_LIFCR_CTCIF0 0x00000020U
#define DMA_LIFCR_CHTIF0 0x00000010U
#define DMA_LIFCR_CTEIF0 0x00000008U
#define DMA_LIFCR_CDMEIF0 0x00000004U
#define DMA_LIFCR_CFEIF0 0x00000001U
/******************** Bits definition for DMA_HIFCR register ****************/
#define DMA_HIFCR_CTCIF7 0x08000000U
#define DMA_HIFCR_CHTIF7 0x04000000U
#define DMA_HIFCR_CTEIF7 0x02000000U
#define DMA_HIFCR_CDMEIF7 0x01000000U
#define DMA_HIFCR_CFEIF7 0x00400000U
#define DMA_HIFCR_CTCIF6 0x00200000U
#define DMA_HIFCR_CHTIF6 0x00100000U
#define DMA_HIFCR_CTEIF6 0x00080000U
#define DMA_HIFCR_CDMEIF6 0x00040000U
#define DMA_HIFCR_CFEIF6 0x00010000U
#define DMA_HIFCR_CTCIF5 0x00000800U
#define DMA_HIFCR_CHTIF5 0x00000400U
#define DMA_HIFCR_CTEIF5 0x00000200U
#define DMA_HIFCR_CDMEIF5 0x00000100U
#define DMA_HIFCR_CFEIF5 0x00000040U
#define DMA_HIFCR_CTCIF4 0x00000020U
#define DMA_HIFCR_CHTIF4 0x00000010U
#define DMA_HIFCR_CTEIF4 0x00000008U
#define DMA_HIFCR_CDMEIF4 0x00000004U
#define DMA_HIFCR_CFEIF4 0x00000001U
/******************************************************************************/
/* */
/* AHB Master DMA2D Controller (DMA2D) */
/* */
/******************************************************************************/
/******************** Bit definition for DMA2D_CR register ******************/
#define DMA2D_CR_START 0x00000001U /*!< Start transfer */
#define DMA2D_CR_SUSP 0x00000002U /*!< Suspend transfer */
#define DMA2D_CR_ABORT 0x00000004U /*!< Abort transfer */
#define DMA2D_CR_TEIE 0x00000100U /*!< Transfer Error Interrupt Enable */
#define DMA2D_CR_TCIE 0x00000200U /*!< Transfer Complete Interrupt Enable */
#define DMA2D_CR_TWIE 0x00000400U /*!< Transfer Watermark Interrupt Enable */
#define DMA2D_CR_CAEIE 0x00000800U /*!< CLUT Access Error Interrupt Enable */
#define DMA2D_CR_CTCIE 0x00001000U /*!< CLUT Transfer Complete Interrupt Enable */
#define DMA2D_CR_CEIE 0x00002000U /*!< Configuration Error Interrupt Enable */
#define DMA2D_CR_MODE 0x00030000U /*!< DMA2D Mode[1:0] */
#define DMA2D_CR_MODE_0 0x00010000U /*!< DMA2D Mode bit 0 */
#define DMA2D_CR_MODE_1 0x00020000U /*!< DMA2D Mode bit 1 */
/******************** Bit definition for DMA2D_ISR register *****************/
#define DMA2D_ISR_TEIF 0x00000001U /*!< Transfer Error Interrupt Flag */
#define DMA2D_ISR_TCIF 0x00000002U /*!< Transfer Complete Interrupt Flag */
#define DMA2D_ISR_TWIF 0x00000004U /*!< Transfer Watermark Interrupt Flag */
#define DMA2D_ISR_CAEIF 0x00000008U /*!< CLUT Access Error Interrupt Flag */
#define DMA2D_ISR_CTCIF 0x00000010U /*!< CLUT Transfer Complete Interrupt Flag */
#define DMA2D_ISR_CEIF 0x00000020U /*!< Configuration Error Interrupt Flag */
/******************** Bit definition for DMA2D_IFCR register ****************/
#define DMA2D_IFCR_CTEIF 0x00000001U /*!< Clears Transfer Error Interrupt Flag */
#define DMA2D_IFCR_CTCIF 0x00000002U /*!< Clears Transfer Complete Interrupt Flag */
#define DMA2D_IFCR_CTWIF 0x00000004U /*!< Clears Transfer Watermark Interrupt Flag */
#define DMA2D_IFCR_CAECIF 0x00000008U /*!< Clears CLUT Access Error Interrupt Flag */
#define DMA2D_IFCR_CCTCIF 0x00000010U /*!< Clears CLUT Transfer Complete Interrupt Flag */
#define DMA2D_IFCR_CCEIF 0x00000020U /*!< Clears Configuration Error Interrupt Flag */
/* Legacy defines */
#define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
#define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
#define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
#define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
#define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
#define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
/******************** Bit definition for DMA2D_FGMAR register ***************/
#define DMA2D_FGMAR_MA 0xFFFFFFFFU /*!< Memory Address */
/******************** Bit definition for DMA2D_FGOR register ****************/
#define DMA2D_FGOR_LO 0x00003FFFU /*!< Line Offset */
/******************** Bit definition for DMA2D_BGMAR register ***************/
#define DMA2D_BGMAR_MA 0xFFFFFFFFU /*!< Memory Address */
/******************** Bit definition for DMA2D_BGOR register ****************/
#define DMA2D_BGOR_LO 0x00003FFFU /*!< Line Offset */
/******************** Bit definition for DMA2D_FGPFCCR register *************/
#define DMA2D_FGPFCCR_CM 0x0000000FU /*!< Input color mode CM[3:0] */
#define DMA2D_FGPFCCR_CM_0 0x00000001U /*!< Input color mode CM bit 0 */
#define DMA2D_FGPFCCR_CM_1 0x00000002U /*!< Input color mode CM bit 1 */
#define DMA2D_FGPFCCR_CM_2 0x00000004U /*!< Input color mode CM bit 2 */
#define DMA2D_FGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
#define DMA2D_FGPFCCR_CCM 0x00000010U /*!< CLUT Color mode */
#define DMA2D_FGPFCCR_START 0x00000020U /*!< Start */
#define DMA2D_FGPFCCR_CS 0x0000FF00U /*!< CLUT size */
#define DMA2D_FGPFCCR_AM 0x00030000U /*!< Alpha mode AM[1:0] */
#define DMA2D_FGPFCCR_AM_0 0x00010000U /*!< Alpha mode AM bit 0 */
#define DMA2D_FGPFCCR_AM_1 0x00020000U /*!< Alpha mode AM bit 1 */
#define DMA2D_FGPFCCR_AI 0x00100000U /*!< Foreground Input Alpha Inverted */
#define DMA2D_FGPFCCR_RBS 0x00200000U /*!< Foreground Input Red Blue Swap */
#define DMA2D_FGPFCCR_ALPHA 0xFF000000U /*!< Alpha value */
/******************** Bit definition for DMA2D_FGCOLR register **************/
#define DMA2D_FGCOLR_BLUE 0x000000FFU /*!< Blue Value */
#define DMA2D_FGCOLR_GREEN 0x0000FF00U /*!< Green Value */
#define DMA2D_FGCOLR_RED 0x00FF0000U /*!< Red Value */
/******************** Bit definition for DMA2D_BGPFCCR register *************/
#define DMA2D_BGPFCCR_CM 0x0000000FU /*!< Input color mode CM[3:0] */
#define DMA2D_BGPFCCR_CM_0 0x00000001U /*!< Input color mode CM bit 0 */
#define DMA2D_BGPFCCR_CM_1 0x00000002U /*!< Input color mode CM bit 1 */
#define DMA2D_BGPFCCR_CM_2 0x00000004U /*!< Input color mode CM bit 2 */
#define DMA2D_FGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
#define DMA2D_BGPFCCR_CCM 0x00000010U /*!< CLUT Color mode */
#define DMA2D_BGPFCCR_START 0x00000020U /*!< Start */
#define DMA2D_BGPFCCR_CS 0x0000FF00U /*!< CLUT size */
#define DMA2D_BGPFCCR_AM 0x00030000U /*!< Alpha mode AM[1:0] */
#define DMA2D_BGPFCCR_AM_0 0x00010000U /*!< Alpha mode AM bit 0 */
#define DMA2D_BGPFCCR_AM_1 0x00020000U /*!< Alpha mode AM bit 1 */
#define DMA2D_BGPFCCR_AI 0x00100000U /*!< background Input Alpha Inverted */
#define DMA2D_BGPFCCR_RBS 0x00200000U /*!< Background Input Red Blue Swap */
#define DMA2D_BGPFCCR_ALPHA 0xFF000000U /*!< background Input Alpha value */
/******************** Bit definition for DMA2D_BGCOLR register **************/
#define DMA2D_BGCOLR_BLUE 0x000000FFU /*!< Blue Value */
#define DMA2D_BGCOLR_GREEN 0x0000FF00U /*!< Green Value */
#define DMA2D_BGCOLR_RED 0x00FF0000U /*!< Red Value */
/******************** Bit definition for DMA2D_FGCMAR register **************/
#define DMA2D_FGCMAR_MA 0xFFFFFFFFU /*!< Memory Address */
/******************** Bit definition for DMA2D_BGCMAR register **************/
#define DMA2D_BGCMAR_MA 0xFFFFFFFFU /*!< Memory Address */
/******************** Bit definition for DMA2D_OPFCCR register **************/
#define DMA2D_OPFCCR_CM 0x00000007U /*!< Color mode CM[2:0] */
#define DMA2D_OPFCCR_CM_0 0x00000001U /*!< Color mode CM bit 0 */
#define DMA2D_OPFCCR_CM_1 0x00000002U /*!< Color mode CM bit 1 */
#define DMA2D_OPFCCR_CM_2 0x00000004U /*!< Color mode CM bit 2 */
#define DMA2D_OPFCCR_AI 0x00100000U /*!< Output Alpha Inverted */
#define DMA2D_OPFCCR_RBS 0x00200000U /*!< Output Red Blue Swap */
/******************** Bit definition for DMA2D_OCOLR register ***************/
/*!<Mode_ARGB8888/RGB888 */
#define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
#define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
#define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
#define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
/*!<Mode_RGB565 */
#define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
#define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
#define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
/*!<Mode_ARGB1555 */
#define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
#define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
#define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
#define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
/*!<Mode_ARGB4444 */
#define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
#define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
#define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
#define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
/******************** Bit definition for DMA2D_OMAR register ****************/
#define DMA2D_OMAR_MA 0xFFFFFFFFU /*!< Memory Address */
/******************** Bit definition for DMA2D_OOR register *****************/
#define DMA2D_OOR_LO 0x00003FFFU /*!< Line Offset */
/******************** Bit definition for DMA2D_NLR register *****************/
#define DMA2D_NLR_NL 0x0000FFFFU /*!< Number of Lines */
#define DMA2D_NLR_PL 0x3FFF0000U /*!< Pixel per Lines */
/******************** Bit definition for DMA2D_LWR register *****************/
#define DMA2D_LWR_LW 0x0000FFFFU /*!< Line Watermark */
/******************** Bit definition for DMA2D_AMTCR register ***************/
#define DMA2D_AMTCR_EN 0x00000001U /*!< Enable */
#define DMA2D_AMTCR_DT 0x0000FF00U /*!< Dead Time */
/******************** Bit definition for DMA2D_FGCLUT register **************/
/******************** Bit definition for DMA2D_BGCLUT register **************/
/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
/******************* Bit definition for EXTI_IMR register *******************/
#define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
#define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
#define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
#define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
#define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
#define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
#define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
#define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
#define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
#define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
#define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
#define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
#define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
#define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
#define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
#define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
#define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
#define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
#define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
#define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
#define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
#define EXTI_IMR_MR23 0x00800000U /*!< Interrupt Mask on line 23 */
#define EXTI_IMR_MR24 0x01000000U /*!< Interrupt Mask on line 24 */
/* Reference Defines */
#define EXTI_IMR_IM0 EXTI_IMR_MR0
#define EXTI_IMR_IM1 EXTI_IMR_MR1
#define EXTI_IMR_IM2 EXTI_IMR_MR2
#define EXTI_IMR_IM3 EXTI_IMR_MR3
#define EXTI_IMR_IM4 EXTI_IMR_MR4
#define EXTI_IMR_IM5 EXTI_IMR_MR5
#define EXTI_IMR_IM6 EXTI_IMR_MR6
#define EXTI_IMR_IM7 EXTI_IMR_MR7
#define EXTI_IMR_IM8 EXTI_IMR_MR8
#define EXTI_IMR_IM9 EXTI_IMR_MR9
#define EXTI_IMR_IM10 EXTI_IMR_MR10
#define EXTI_IMR_IM11 EXTI_IMR_MR11
#define EXTI_IMR_IM12 EXTI_IMR_MR12
#define EXTI_IMR_IM13 EXTI_IMR_MR13
#define EXTI_IMR_IM14 EXTI_IMR_MR14
#define EXTI_IMR_IM15 EXTI_IMR_MR15
#define EXTI_IMR_IM16 EXTI_IMR_MR16
#define EXTI_IMR_IM17 EXTI_IMR_MR17
#define EXTI_IMR_IM18 EXTI_IMR_MR18
#define EXTI_IMR_IM19 EXTI_IMR_MR19
#define EXTI_IMR_IM20 EXTI_IMR_MR20
#define EXTI_IMR_IM21 EXTI_IMR_MR21
#define EXTI_IMR_IM22 EXTI_IMR_MR22
#define EXTI_IMR_IM23 EXTI_IMR_MR23
#define EXTI_IMR_IM24 EXTI_IMR_MR24
#define EXTI_IMR_IM 0x01FFFFFFU /*!< Interrupt Mask All */
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
#define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
#define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
#define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
#define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
#define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
#define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
#define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
#define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
#define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
#define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
#define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
#define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
#define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
#define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
#define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
#define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
#define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
#define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
#define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
#define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
#define EXTI_EMR_MR23 0x00800000U /*!< Event Mask on line 23 */
#define EXTI_EMR_MR24 0x01000000U /*!< Event Mask on line 24 */
/* Reference Defines */
#define EXTI_EMR_EM0 EXTI_EMR_MR0
#define EXTI_EMR_EM1 EXTI_EMR_MR1
#define EXTI_EMR_EM2 EXTI_EMR_MR2
#define EXTI_EMR_EM3 EXTI_EMR_MR3
#define EXTI_EMR_EM4 EXTI_EMR_MR4
#define EXTI_EMR_EM5 EXTI_EMR_MR5
#define EXTI_EMR_EM6 EXTI_EMR_MR6
#define EXTI_EMR_EM7 EXTI_EMR_MR7
#define EXTI_EMR_EM8 EXTI_EMR_MR8
#define EXTI_EMR_EM9 EXTI_EMR_MR9
#define EXTI_EMR_EM10 EXTI_EMR_MR10
#define EXTI_EMR_EM11 EXTI_EMR_MR11
#define EXTI_EMR_EM12 EXTI_EMR_MR12
#define EXTI_EMR_EM13 EXTI_EMR_MR13
#define EXTI_EMR_EM14 EXTI_EMR_MR14
#define EXTI_EMR_EM15 EXTI_EMR_MR15
#define EXTI_EMR_EM16 EXTI_EMR_MR16
#define EXTI_EMR_EM17 EXTI_EMR_MR17
#define EXTI_EMR_EM18 EXTI_EMR_MR18
#define EXTI_EMR_EM19 EXTI_EMR_MR19
#define EXTI_EMR_EM20 EXTI_EMR_MR20
#define EXTI_EMR_EM21 EXTI_EMR_MR21
#define EXTI_EMR_EM22 EXTI_EMR_MR22
#define EXTI_EMR_EM23 EXTI_EMR_MR23
#define EXTI_EMR_EM24 EXTI_EMR_MR24
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
#define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
#define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
#define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
#define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
#define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
#define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
#define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
#define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
#define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
#define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
#define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
#define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
#define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
#define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
#define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
#define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
#define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
#define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
#define EXTI_RTSR_TR23 0x00800000U /*!< Rising trigger event configuration bit of line 23 */
#define EXTI_RTSR_TR24 0x01000000U /*!< Rising trigger event configuration bit of line 24 */
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
#define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
#define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
#define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
#define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
#define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
#define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
#define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
#define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
#define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
#define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
#define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
#define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
#define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
#define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
#define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
#define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
#define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
#define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
#define EXTI_FTSR_TR23 0x00800000U /*!< Falling trigger event configuration bit of line 23 */
#define EXTI_FTSR_TR24 0x01000000U /*!< Falling trigger event configuration bit of line 24 */
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 0x00000001U /*!< Software I