example

STM32F405-Timer-Triggering.md

@@ -1,5 +1,27 @@
 The Timers can be cascaded to make more complex timing relationships, or longer periods.
-Internally only some timers can trigger others. THis is in a master slave relationship and is handled by teh SMS register.
+Internally only some timers can trigger others. This is a Master/Slave relationship and is handled by the SMS register.
+
+For example, you can see below that TIM8 can be triggerd by TIM1.
 
 ![Timer Master/Slave relationships](http://i59.tinypic.com/2ptpab5.jpg)
 
+* One Timer can be used as the prescaler for another.
+* The first timer update_event, or output_compare signal is used as clock for the second.
+* Uses TRGI to map.
+* Counter mode is set using the TIMx_CR1 reg and CMS bits as indicated in the example below.
+* The counter mode sets whether the update_event occurs on overflow and/or underflow of the Timer.
+
+###Example for internal trigger
+Internal trigger clock mode 1 (ITRx)
+TIM_CLK is replaced by ITRx_CLK which is the internal trigger freq mapped to timer Trigger input TRGI.
+
+The counter mode indicates if the update_event is generated:
+* on overflow - if mode = up counting, the DIR bit is reset in TIMx_CR1
+* on underlfow - if mode = down counting, the DIR bit is set in TIMx_CR1
+* both - if mode is center aligned, the CMS bits are non zero
+
+The update_event is also generated by:
+* software if the UG bit (Update Generation) is set in TIM_EGR reg.
+* update generation through the slave mode controller
+
+refer to Timer app note: DM00042534.pdf