168 lines
6.5 KiB
Plaintext
168 lines
6.5 KiB
Plaintext
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; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
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;
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; SPDX-License-Identifier: BSD-3-Clause
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;
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; These programs implement full-duplex SPI, with a SCK period of 4 clock
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; cycles. A different program is provided for each value of CPHA, and CPOL is
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; achieved using the hardware GPIO inversion available in the IO controls.
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;
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; Transmit-only SPI can go twice as fast -- see the ST7789 example!
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.program spi_cpha0
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.side_set 1
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; Pin assignments:
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; - SCK is side-set pin 0
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; - MOSI is OUT pin 0
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; - MISO is IN pin 0
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;
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; Autopush and autopull must be enabled, and the serial frame size is set by
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; configuring the push/pull threshold. Shift left/right is fine, but you must
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; justify the data yourself. This is done most conveniently for frame sizes of
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; 8 or 16 bits by using the narrow store replication and narrow load byte
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; picking behaviour of RP2040's IO fabric.
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; Clock phase = 0: data is captured on the leading edge of each SCK pulse, and
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; transitions on the trailing edge, or some time before the first leading edge.
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out pins, 1 side 0 [1] ; Stall here on empty (sideset proceeds even if
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in pins, 1 side 1 [1] ; instruction stalls, so we stall with SCK low)
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.program spi_cpha1
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.side_set 1
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; Clock phase = 1: data transitions on the leading edge of each SCK pulse, and
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; is captured on the trailing edge.
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out x, 1 side 0 ; Stall here on empty (keep SCK deasserted)
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mov pins, x side 1 [1] ; Output data, assert SCK (mov pins uses OUT mapping)
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in pins, 1 side 0 ; Input data, deassert SCK
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% c-sdk {
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#include "hardware/gpio.h"
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static inline void pio_spi_init(PIO pio, uint sm, uint prog_offs, uint n_bits,
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float clkdiv, bool cpha, bool cpol, uint pin_sck, uint pin_mosi, uint pin_miso) {
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pio_sm_config c = cpha ? spi_cpha1_program_get_default_config(prog_offs) : spi_cpha0_program_get_default_config(prog_offs);
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sm_config_set_out_pins(&c, pin_mosi, 1);
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sm_config_set_in_pins(&c, pin_miso);
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sm_config_set_sideset_pins(&c, pin_sck);
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// Only support MSB-first in this example code (shift to left, auto push/pull, threshold=nbits)
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sm_config_set_out_shift(&c, false, true, n_bits);
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sm_config_set_in_shift(&c, false, true, n_bits);
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sm_config_set_clkdiv(&c, clkdiv);
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// MOSI, SCK output are low, MISO is input
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pio_sm_set_pins_with_mask(pio, sm, 0, (1u << pin_sck) | (1u << pin_mosi));
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pio_sm_set_pindirs_with_mask(pio, sm, (1u << pin_sck) | (1u << pin_mosi), (1u << pin_sck) | (1u << pin_mosi) | (1u << pin_miso));
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pio_gpio_init(pio, pin_mosi);
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pio_gpio_init(pio, pin_miso);
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pio_gpio_init(pio, pin_sck);
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// The pin muxes can be configured to invert the output (among other things
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// and this is a cheesy way to get CPOL=1
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gpio_set_outover(pin_sck, cpol ? GPIO_OVERRIDE_INVERT : GPIO_OVERRIDE_NORMAL);
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// SPI is synchronous, so bypass input synchroniser to reduce input delay.
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hw_set_bits(&pio->input_sync_bypass, 1u << pin_miso);
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pio_sm_init(pio, sm, prog_offs, &c);
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pio_sm_set_enabled(pio, sm, true);
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}
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%}
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; SPI with Chip Select
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; -----------------------------------------------------------------------------
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;
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; For your amusement, here are some SPI programs with an automatic chip select
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; (asserted once data appears in TX FIFO, deasserts when FIFO bottoms out, has
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; a nice front/back porch).
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;
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; The number of bits per FIFO entry is configured via the Y register
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; and the autopush/pull threshold. From 2 to 32 bits.
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;
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; Pin assignments:
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; - SCK is side-set bit 0
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; - CSn is side-set bit 1
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; - MOSI is OUT bit 0 (host-to-device)
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; - MISO is IN bit 0 (device-to-host)
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;
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; This program only supports one chip select -- use GPIO if more are needed
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;
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; Provide a variation for each possibility of CPHA; for CPOL we can just
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; invert SCK in the IO muxing controls (downstream from PIO)
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; CPHA=0: data is captured on the leading edge of each SCK pulse (including
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; the first pulse), and transitions on the trailing edge
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.program spi_cpha0_cs
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.side_set 2
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.wrap_target
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bitloop:
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out pins, 1 side 0x0 [1]
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in pins, 1 side 0x1
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jmp x-- bitloop side 0x1
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out pins, 1 side 0x0
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mov x, y side 0x0 ; Reload bit counter from Y
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in pins, 1 side 0x1
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jmp !osre bitloop side 0x1 ; Fall-through if TXF empties
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nop side 0x0 [1] ; CSn back porch
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public entry_point: ; Must set X,Y to n-2 before starting!
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pull ifempty side 0x2 [1] ; Block with CSn high (minimum 2 cycles)
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.wrap ; Note ifempty to avoid time-of-check race
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; CPHA=1: data transitions on the leading edge of each SCK pulse, and is
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; captured on the trailing edge
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.program spi_cpha1_cs
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.side_set 2
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.wrap_target
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bitloop:
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out pins, 1 side 0x1 [1]
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in pins, 1 side 0x0
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jmp x-- bitloop side 0x0
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out pins, 1 side 0x1
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mov x, y side 0x1
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in pins, 1 side 0x0
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jmp !osre bitloop side 0x0
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public entry_point: ; Must set X,Y to n-2 before starting!
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pull ifempty side 0x2 [1] ; Block with CSn high (minimum 2 cycles)
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nop side 0x0 [1]; CSn front porch
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.wrap
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% c-sdk {
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#include "hardware/gpio.h"
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static inline void pio_spi_cs_init(PIO pio, uint sm, uint prog_offs, uint n_bits, float clkdiv, bool cpha, bool cpol,
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uint pin_sck, uint pin_mosi, uint pin_miso) {
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pio_sm_config c = cpha ? spi_cpha1_cs_program_get_default_config(prog_offs) : spi_cpha0_cs_program_get_default_config(prog_offs);
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sm_config_set_out_pins(&c, pin_mosi, 1);
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sm_config_set_in_pins(&c, pin_miso);
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sm_config_set_sideset_pins(&c, pin_sck);
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sm_config_set_out_shift(&c, false, true, n_bits);
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sm_config_set_in_shift(&c, false, true, n_bits);
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sm_config_set_clkdiv(&c, clkdiv);
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pio_sm_set_pins_with_mask(pio, sm, (2u << pin_sck), (3u << pin_sck) | (1u << pin_mosi));
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pio_sm_set_pindirs_with_mask(pio, sm, (3u << pin_sck) | (1u << pin_mosi), (3u << pin_sck) | (1u << pin_mosi) | (1u << pin_miso));
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pio_gpio_init(pio, pin_mosi);
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pio_gpio_init(pio, pin_miso);
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pio_gpio_init(pio, pin_sck);
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pio_gpio_init(pio, pin_sck + 1);
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gpio_set_outover(pin_sck, cpol ? GPIO_OVERRIDE_INVERT : GPIO_OVERRIDE_NORMAL);
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hw_set_bits(&pio->input_sync_bypass, 1u << pin_miso);
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uint entry_point = prog_offs + (cpha ? spi_cpha1_cs_offset_entry_point : spi_cpha0_cs_offset_entry_point);
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pio_sm_init(pio, sm, entry_point, &c);
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pio_sm_exec(pio, sm, pio_encode_set(pio_x, n_bits - 2));
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pio_sm_exec(pio, sm, pio_encode_set(pio_y, n_bits - 2));
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pio_sm_set_enabled(pio, sm, true);
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}
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%}
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