2021-05-11 13:00:12 +01:00
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#include <cstdlib>
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#include <math.h>
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#include <map>
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#include <vector>
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2021-05-11 17:18:43 +01:00
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#include "ioexpander.hpp"
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2021-05-11 13:00:12 +01:00
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namespace pimoroni {
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enum reg {
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CHIP_ID_L = 0xfa,
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CHIP_ID_H = 0xfb,
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VERSION = 0xfc,
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// Rotary encoder
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ENC_EN = 0x04,
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// BIT_ENC_EN_1 = 0
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// BIT_ENC_MICROSTEP_1 = 1
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// BIT_ENC_EN_2 = 2
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// BIT_ENC_MICROSTEP_2 = 3
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// BIT_ENC_EN_3 = 4
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// BIT_ENC_MICROSTEP_3 = 5
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// BIT_ENC_EN_4 = 6
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// BIT_ENC_MICROSTEP_4 = 7
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ENC_1_CFG = 0x05,
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ENC_1_COUNT = 0x06,
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ENC_2_CFG = 0x07,
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ENC_2_COUNT = 0x08,
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ENC_3_CFG = 0x09,
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ENC_3_COUNT = 0x0A,
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ENC_4_CFG = 0x0B,
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ENC_4_COUNT = 0x0C,
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// Cap touch
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CAPTOUCH_EN = 0x0D,
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CAPTOUCH_CFG = 0x0E,
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CAPTOUCH_0 = 0x0F, // First of 8 bytes from 15-22
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// Switch counters
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SWITCH_EN_P0 = 0x17,
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SWITCH_EN_P1 = 0x18,
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SWITCH_P00 = 0x19, // First of 8 bytes from 25-40
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SWITCH_P10 = 0x21, // First of 8 bytes from 33-49
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USER_FLASH = 0xD0,
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FLASH_PAGE = 0xF0,
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DEBUG = 0xF8,
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P0 = 0x40, // protect_bits 2 # Bit addressing
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SP = 0x41, // Read only
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DPL = 0x42, // Read only
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DPH = 0x43, // Read only
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RCTRIM0 = 0x44, // Read only
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RCTRIM1 = 0x45, // Read only
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RWK = 0x46,
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PCON = 0x47, // Read only
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TCON = 0x48,
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TMOD = 0x49,
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TL0 = 0x4a,
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TL1 = 0x4b,
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TH0 = 0x4c,
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TH1 = 0x4d,
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CKCON = 0x4e,
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WKCON = 0x4f, // Read only
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P1 = 0x50, // protect_bits 3 6 # Bit addressing
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SFRS = 0x51, // TA protected # Read only
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CAPCON0 = 0x52,
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CAPCON1 = 0x53,
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CAPCON2 = 0x54,
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CKDIV = 0x55,
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CKSWT = 0x56, // TA protected # Read only
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CKEN = 0x57, // TA protected # Read only
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SCON = 0x58,
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SBUF = 0x59,
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SBUF_1 = 0x5a,
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EIE = 0x5b, // Read only
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EIE1 = 0x5c, // Read only
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CHPCON = 0x5f, // TA protected # Read only
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P2 = 0x60, // Bit addressing
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AUXR1 = 0x62,
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BODCON0 = 0x63, // TA protected
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IAPTRG = 0x64, // TA protected # Read only
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IAPUEN = 0x65, // TA protected # Read only
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IAPAL = 0x66, // Read only
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IAPAH = 0x67, // Read only
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IE = 0x68, // Read only
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SADDR = 0x69,
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WDCON = 0x6a, // TA protected
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BODCON1 = 0x6b, // TA protected
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P3M1 = 0x6c,
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P3S = 0xc0, // Page 1 # Reassigned from 0x6c to avoid collision
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P3M2 = 0x6d,
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P3SR = 0xc1, // Page 1 # Reassigned from 0x6d to avoid collision
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IAPFD = 0x6e, // Read only
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IAPCN = 0x6f, // Read only
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P3 = 0x70, // Bit addressing
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P0M1 = 0x71, // protect_bits 2
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P0S = 0xc2, // Page 1 # Reassigned from 0x71 to avoid collision
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P0M2 = 0x72, // protect_bits 2
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P0SR = 0xc3, // Page 1 # Reassigned from 0x72 to avoid collision
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P1M1 = 0x73, // protect_bits 3 6
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P1S = 0xc4, // Page 1 # Reassigned from 0x73 to avoid collision
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P1M2 = 0x74, // protect_bits 3 6
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P1SR = 0xc5, // Page 1 # Reassigned from 0x74 to avoid collision
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P2S = 0x75,
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IPH = 0x77, // Read only
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PWMINTC = 0xc6, // Page 1 # Read only # Reassigned from 0x77 to avoid collision
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IP = 0x78, // Read only
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SADEN = 0x79,
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SADEN_1 = 0x7a,
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SADDR_1 = 0x7b,
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I2DAT = 0x7c, // Read only
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I2STAT = 0x7d, // Read only
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I2CLK = 0x7e, // Read only
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I2TOC = 0x7f, // Read only
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I2CON = 0x80, // Read only
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I2ADDR = 0x81, // Read only
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ADCRL = 0x82,
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ADCRH = 0x83,
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T3CON = 0x84,
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PWM4H = 0xc7, // Page 1 # Reassigned from 0x84 to avoid collision
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RL3 = 0x85,
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PWM5H = 0xc8, // Page 1 # Reassigned from 0x85 to avoid collision
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RH3 = 0x86,
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PIOCON1 = 0xc9, // Page 1 # Reassigned from 0x86 to avoid collision
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TA = 0x87, // Read only
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T2CON = 0x88,
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T2MOD = 0x89,
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RCMP2L = 0x8a,
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RCMP2H = 0x8b,
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TL2 = 0x8c,
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PWM4L = 0xca, // Page 1 # Reassigned from 0x8c to avoid collision
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TH2 = 0x8d,
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PWM5L = 0xcb, // Page 1 # Reassigned from 0x8d to avoid collision
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ADCMPL = 0x8e,
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ADCMPH = 0x8f,
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PSW = 0x90, // Read only
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PWMPH = 0x91,
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PWM0H = 0x92,
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PWM1H = 0x93,
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PWM2H = 0x94,
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PWM3H = 0x95,
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PNP = 0x96,
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FBD = 0x97,
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PWMCON0 = 0x98,
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PWMPL = 0x99,
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PWM0L = 0x9a,
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PWM1L = 0x9b,
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PWM2L = 0x9c,
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PWM3L = 0x9d,
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PIOCON0 = 0x9e,
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PWMCON1 = 0x9f,
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ACC = 0xa0, // Read only
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ADCCON1 = 0xa1,
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ADCCON2 = 0xa2,
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ADCDLY = 0xa3,
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C0L = 0xa4,
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C0H = 0xa5,
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C1L = 0xa6,
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C1H = 0xa7,
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ADCCON0 = 0xa8,
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PICON = 0xa9, // Read only
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PINEN = 0xaa, // Read only
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PIPEN = 0xab, // Read only
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PIF = 0xac, // Read only
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C2L = 0xad,
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C2H = 0xae,
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EIP = 0xaf, // Read only
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B = 0xb0, // Read only
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CAPCON3 = 0xb1,
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CAPCON4 = 0xb2,
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SPCR = 0xb3,
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SPCR2 = 0xcc, // Page 1 # Reassigned from 0xb3 to avoid collision
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SPSR = 0xb4,
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SPDR = 0xb5,
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AINDIDS = 0xb6,
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EIPH = 0xb7, // Read only
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SCON_1 = 0xb8,
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PDTEN = 0xb9, // TA protected
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PDTCNT = 0xba, // TA protected
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PMEN = 0xbb,
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PMD = 0xbc,
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EIP1 = 0xbe, // Read only
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EIPH1 = 0xbf, // Read only
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INT = 0xf9,
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INT_MASK_P0 = 0x00,
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INT_MASK_P1 = 0x01,
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INT_MASK_P3 = 0x03,
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ADDR = 0xfd,
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CTRL = 0xfe, // 0 = Sleep, 1 = Reset, 2 = Read Flash, 3 = Write Flash, 4 = Addr Unlock
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};
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enum int_mask {
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TRIG = 0x1,
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OUT = 0x2,
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};
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enum int_bit {
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TRIGD = 0,
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OUT_EN = 1,
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PIN_SWAP = 2, // 0 = P1.3, 1 = P0.0
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};
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enum ctrl_mask {
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SLEEP = 0x1,
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RESET = 0x2,
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FREAD = 0x4,
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FWRITE = 0x8,
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ADDRWR = 0x10,
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};
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static const uint8_t NUM_BIT_ADDRESSED_REGISTERS = 4;
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static const uint8_t BIT_ADDRESSED_REGS[NUM_BIT_ADDRESSED_REGISTERS] = {reg::P0, reg::P1, reg::P2, reg::P3};
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static const uint8_t ENC_CFG[4] = {reg::ENC_1_CFG, reg::ENC_2_CFG, reg::ENC_3_CFG, reg::ENC_4_CFG};
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static const uint8_t ENC_COUNT[4] = {reg::ENC_1_COUNT, reg::ENC_2_COUNT, reg::ENC_3_COUNT, reg::ENC_4_COUNT};
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const uint8_t IOExpander::Pin::PxM1[4] = {reg::P0M1, reg::P1M1, (uint8_t)-1, reg::P3M1};
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const uint8_t IOExpander::Pin::PxM2[4] = {reg::P0M2, reg::P1M2, (uint8_t)-1, reg::P3M2};
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const uint8_t IOExpander::Pin::Px[4] = {reg::P0, reg::P1, (uint8_t)-1, reg::P3};
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const uint8_t IOExpander::Pin::PxS[4] = {reg::P0S, reg::P1S, (uint8_t)-1, reg::P3S};
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const uint8_t IOExpander::Pin::MASK_P[4] = {reg::INT_MASK_P0, reg::INT_MASK_P1, (uint8_t)-1, reg::INT_MASK_P3};
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const uint8_t IOExpander::Pin::PWML[6] = {reg::PWM0L, reg::PWM1L, reg::PWM2L, reg::PWM3L, reg::PWM4L, reg::PWM5L};
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const uint8_t IOExpander::Pin::PWMH[6] = {reg::PWM0H, reg::PWM1H, reg::PWM2H, reg::PWM3H, reg::PWM4H, reg::PWM5H};
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static const char* MODE_NAMES[3] = {"IO", "PWM", "ADC"};
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static const char* GPIO_NAMES[4] = {"QB", "PP", "IN", "OD"};
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static const char* STATE_NAMES[2] = {"LOW", "HIGH"};
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IOExpander::Pin::Pin(uint8_t port, uint8_t pin) :
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type(TYPE_IO), mode(0), port(port), pin(pin), adc_channel(0), pwm_channel(0),
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reg_m1(PxM1[port]), reg_m2(PxM2[port]), reg_p(Px[port]), reg_ps(PxS[port]), reg_int_mask_p(MASK_P[port]),
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reg_io_pwm(0), reg_pwml(0), reg_pwmh(0) {
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}
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2021-05-11 17:18:43 +01:00
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IOExpander::Pin::Pin(uint8_t port, uint8_t pin, uint8_t pwm_channel, uint8_t reg_io_pwm) :
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type(TYPE_PWM), mode(0), port(port), pin(pin), adc_channel(0), pwm_channel(pwm_channel),
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reg_m1(PxM1[port]), reg_m2(PxM2[port]), reg_p(Px[port]), reg_ps(PxS[port]), reg_int_mask_p(MASK_P[port]),
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reg_io_pwm(reg_io_pwm), reg_pwml(PWML[pwm_channel]), reg_pwmh(PWMH[pwm_channel]) {
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}
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IOExpander::Pin::Pin(uint8_t port, uint8_t pin, uint8_t adc_channel) :
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type(TYPE_ADC), mode(0), port(port), pin(pin), adc_channel(adc_channel), pwm_channel(0),
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reg_m1(PxM1[port]), reg_m2(PxM2[port]), reg_p(Px[port]), reg_ps(PxS[port]), reg_int_mask_p(MASK_P[port]),
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reg_io_pwm(0), reg_pwml(0), reg_pwmh(0) {
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}
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IOExpander::Pin::Pin(uint8_t port, uint8_t pin, uint8_t adc_channel, uint8_t pwm_channel, uint8_t reg_io_pwm) :
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type(TYPE_ADC_OR_PWM), mode(0), port(port), pin(pin), adc_channel(adc_channel), pwm_channel(pwm_channel),
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reg_m1(PxM1[port]), reg_m2(PxM2[port]), reg_p(Px[port]), reg_ps(PxS[port]), reg_int_mask_p(MASK_P[port]),
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reg_io_pwm(reg_io_pwm), reg_pwml(PWML[pwm_channel]), reg_pwmh(PWMH[pwm_channel]) {
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}
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IOExpander::Pin IOExpander::Pin::io(uint8_t port, uint8_t pin) {
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return Pin(port, pin);
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}
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2021-05-11 17:18:43 +01:00
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IOExpander::Pin IOExpander::Pin::pwm(uint8_t port, uint8_t pin, uint8_t channel, uint8_t reg_iopwm) {
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return Pin(port, pin, channel, reg_iopwm);
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}
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IOExpander::Pin IOExpander::Pin::adc(uint8_t port, uint8_t pin, uint8_t channel) {
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return Pin(port, pin, channel);
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}
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IOExpander::Pin IOExpander::Pin::adc_or_pwm(uint8_t port, uint8_t pin, uint8_t adc_channel, uint8_t pwm_channel, uint8_t reg_iopwm) {
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return Pin(port, pin, adc_channel, pwm_channel, reg_iopwm);
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}
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bool IOExpander::Pin::mode_supported(uint8_t mode) {
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bool supported = false;
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if((type & TYPE_PWM) && (mode == PIN_MODE_PWM)) {
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supported = true;
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}
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else if((type & TYPE_ADC) && (mode == PIN_MODE_ADC)) {
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supported = true;
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}
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return supported;
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}
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IOExpander::Pin::IOType IOExpander::Pin::get_type() {
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return type;
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}
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uint8_t IOExpander::Pin::get_mode() {
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2021-05-11 13:00:12 +01:00
|
|
|
return mode;
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
void IOExpander::Pin::set_mode(uint8_t mode) {
|
2021-05-11 13:00:12 +01:00
|
|
|
this->mode = mode;
|
|
|
|
}
|
|
|
|
|
2021-05-11 20:08:04 +01:00
|
|
|
IOExpander::IOExpander() :
|
|
|
|
IOExpander(i2c0, DEFAULT_I2C_ADDRESS, DEFAULT_SDA_PIN, DEFAULT_SCL_PIN, DEFAULT_INT_PIN) {
|
|
|
|
}
|
|
|
|
|
|
|
|
IOExpander::IOExpander(uint8_t address, uint32_t timeout, bool debug) :
|
|
|
|
IOExpander(i2c0, address, DEFAULT_SDA_PIN, DEFAULT_SCL_PIN, DEFAULT_INT_PIN, timeout, debug) {
|
|
|
|
}
|
|
|
|
|
|
|
|
IOExpander::IOExpander(i2c_inst_t *i2c, uint8_t address, uint8_t sda, uint8_t scl, uint8_t interrupt, uint32_t timeout, bool debug) :
|
|
|
|
i2c(i2c), address(address), sda(sda), scl(scl), interrupt(interrupt),
|
|
|
|
timeout(timeout), debug(debug), vref(3.3f),
|
2021-05-11 13:00:12 +01:00
|
|
|
encoder_offset{0,0,0,0},
|
|
|
|
encoder_last{0,0,0,0},
|
|
|
|
pins{ Pin::pwm(1, 5, 5, reg::PIOCON1),
|
|
|
|
Pin::pwm(1, 0, 2, reg::PIOCON0),
|
|
|
|
Pin::pwm(1, 2, 0, reg::PIOCON0),
|
|
|
|
Pin::pwm(1, 4, 1, reg::PIOCON1),
|
|
|
|
Pin::pwm(0, 0, 3, reg::PIOCON0),
|
|
|
|
Pin::pwm(0, 1, 4, reg::PIOCON0),
|
|
|
|
Pin::adc_or_pwm(1, 1, 7, 1, reg::PIOCON0),
|
|
|
|
Pin::adc_or_pwm(0, 3, 6, 5, reg::PIOCON0),
|
|
|
|
Pin::adc_or_pwm(0, 4, 5, 3, reg::PIOCON1),
|
|
|
|
Pin::adc(3, 0, 1),
|
|
|
|
Pin::adc(0, 6, 3),
|
|
|
|
Pin::adc_or_pwm(0, 5, 4, 2, reg::PIOCON1),
|
|
|
|
Pin::adc(0, 7, 2),
|
|
|
|
Pin::adc(1, 7, 0)} {
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
bool IOExpander::init(bool skipChipIdCheck) {
|
2021-05-11 13:00:12 +01:00
|
|
|
bool succeeded = true;
|
|
|
|
|
|
|
|
i2c_init(i2c, 400000);
|
|
|
|
|
|
|
|
gpio_set_function(sda, GPIO_FUNC_I2C); gpio_pull_up(sda);
|
|
|
|
gpio_set_function(scl, GPIO_FUNC_I2C); gpio_pull_up(scl);
|
|
|
|
|
|
|
|
if(interrupt != -1) {
|
|
|
|
gpio_set_function(interrupt, GPIO_FUNC_SIO); gpio_set_dir(interrupt, GPIO_IN); gpio_pull_up(interrupt);
|
|
|
|
enable_interrupt_out(true);
|
|
|
|
}
|
|
|
|
|
|
|
|
if(!skipChipIdCheck) {
|
|
|
|
uint16_t chip_id = get_chip_id();
|
|
|
|
if(chip_id != CHIP_ID) {
|
|
|
|
if(debug) {
|
|
|
|
printf("Chip ID invalid: %04x expected: %04x\n", chip_id, CHIP_ID);
|
|
|
|
}
|
|
|
|
succeeded = false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return succeeded;
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
i2c_inst_t* IOExpander::get_i2c() const {
|
|
|
|
return i2c;
|
|
|
|
}
|
|
|
|
|
|
|
|
int IOExpander::get_sda() const {
|
|
|
|
return sda;
|
|
|
|
}
|
|
|
|
|
|
|
|
int IOExpander::get_scl() const {
|
|
|
|
return scl;
|
|
|
|
}
|
|
|
|
|
|
|
|
int IOExpander::get_int() const {
|
|
|
|
return interrupt;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint16_t IOExpander::get_chip_id() {
|
2021-05-11 13:00:12 +01:00
|
|
|
return ((uint16_t)i2c_reg_read_uint8(reg::CHIP_ID_H) << 8) | (uint16_t)i2c_reg_read_uint8(reg::CHIP_ID_L);
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
void IOExpander::set_addr(uint8_t address) {
|
2021-05-11 13:00:12 +01:00
|
|
|
set_bit(reg::CTRL, 4);
|
|
|
|
i2c_reg_write_uint8(reg::ADDR, address);
|
|
|
|
this->address = address;
|
|
|
|
sleep_ms(250); //TODO Handle addr change IOError better
|
|
|
|
//wait_for_flash()
|
|
|
|
clr_bit(reg::CTRL, 4);
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
float IOExpander::get_adc_vref() {
|
2021-05-11 13:00:12 +01:00
|
|
|
return vref;
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
void IOExpander::set_adc_vref(float vref) {
|
2021-05-11 13:00:12 +01:00
|
|
|
this->vref = vref;
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
void IOExpander::enable_interrupt_out(bool pin_swap) {
|
2021-05-11 13:00:12 +01:00
|
|
|
set_bit(reg::INT, int_bit::OUT_EN);
|
|
|
|
change_bit(reg::INT, int_bit::PIN_SWAP, pin_swap);
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
void IOExpander::disable_interrupt_out() {
|
2021-05-11 13:00:12 +01:00
|
|
|
clr_bit(reg::INT, int_bit::OUT_EN);
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
uint8_t IOExpander::get_interrupt_flag() {
|
2021-05-11 13:00:12 +01:00
|
|
|
if(interrupt != 0)
|
|
|
|
return !gpio_get(interrupt);
|
|
|
|
else
|
|
|
|
return get_bit(reg::INT, int_bit::TRIGD);
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
void IOExpander::clear_interrupt_flag() {
|
2021-05-11 13:00:12 +01:00
|
|
|
clr_bit(reg::INT, int_bit::TRIGD);
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
bool IOExpander::set_pin_interrupt(uint8_t pin, bool enabled) {
|
2021-05-11 13:00:12 +01:00
|
|
|
bool succeeded = false;
|
|
|
|
if(pin >= 1 && pin <= NUM_PINS) {
|
|
|
|
Pin& io_pin = pins[pin - 1];
|
|
|
|
change_bit(io_pin.reg_int_mask_p, io_pin.pin, enabled);
|
|
|
|
|
|
|
|
succeeded = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return succeeded;
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
void IOExpander::set_interrupt_callback(void (*callback)()) {
|
2021-05-11 13:00:12 +01:00
|
|
|
if(interrupt != 0 && callback != nullptr) {
|
|
|
|
//attachInterrupt(digitalPinToInterrupt(_interruptPin), callback, FALLING);
|
|
|
|
clear_interrupt_flag();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
void IOExpander::pwm_load(bool wait_for_load) {
|
2021-05-11 13:00:12 +01:00
|
|
|
//Load new period and duty registers into buffer
|
|
|
|
uint32_t start_time = millis();
|
|
|
|
set_bit(reg::PWMCON0, 6); //Set the "LOAD" bit of PWMCON0
|
|
|
|
|
|
|
|
if(wait_for_load) {
|
|
|
|
while(pwm_loading()) {
|
|
|
|
sleep_ms(1); //Wait for "LOAD" to complete
|
|
|
|
if(millis() - start_time >= timeout) {
|
|
|
|
if(debug)
|
|
|
|
printf("Timed out waiting for PWM load!");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
bool IOExpander::pwm_loading() {
|
2021-05-11 13:00:12 +01:00
|
|
|
return get_bit(reg::PWMCON0, 6);
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
void IOExpander::pwm_clear(bool wait_for_clear) {
|
2021-05-11 13:00:12 +01:00
|
|
|
uint32_t start_time = millis();
|
|
|
|
set_bit(reg::PWMCON0, 4); //Set the "CLRPWM" bit of PWMCON0
|
|
|
|
if(wait_for_clear) {
|
|
|
|
while(pwm_clearing()) {
|
|
|
|
sleep_ms(1); //Wait for "CLRPWM" to complete
|
|
|
|
if(millis() - start_time >= timeout) {
|
|
|
|
if(debug)
|
|
|
|
printf("Timed out waiting for PWM clear!");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
bool IOExpander::pwm_clearing() {
|
2021-05-11 13:00:12 +01:00
|
|
|
return get_bit(reg::PWMCON0, 4);
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
bool IOExpander::set_pwm_control(uint8_t divider) {
|
2021-05-11 13:00:12 +01:00
|
|
|
bool divider_good = true;
|
|
|
|
uint8_t pwmdiv2 = 0;
|
|
|
|
switch(divider) {
|
|
|
|
case 1: pwmdiv2 = 0b000; break;
|
|
|
|
case 2: pwmdiv2 = 0b001; break;
|
|
|
|
case 4: pwmdiv2 = 0b010; break;
|
|
|
|
case 8: pwmdiv2 = 0b011; break;
|
|
|
|
case 16: pwmdiv2 = 0b100; break;
|
|
|
|
case 32: pwmdiv2 = 0b101; break;
|
|
|
|
case 64: pwmdiv2 = 0b110; break;
|
|
|
|
case 128: pwmdiv2 = 0b111; break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
if(debug) {
|
|
|
|
printf("ValueError: A clock divider of %d\n", divider);
|
|
|
|
}
|
|
|
|
divider_good = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if(divider_good) {
|
|
|
|
//TODO: This currently sets GP, PWMTYP and FBINEN to 0
|
|
|
|
//It might be desirable to make these available to the user
|
|
|
|
//GP - Group mode enable (changes first three pairs of pAM to PWM01H and PWM01L)
|
|
|
|
//PWMTYP - PWM type select: 0 edge-aligned, 1 center-aligned
|
|
|
|
//FBINEN - Fault-break input enable
|
|
|
|
|
|
|
|
i2c_reg_write_uint8(reg::PWMCON1, pwmdiv2);
|
|
|
|
}
|
|
|
|
|
|
|
|
return divider_good;
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
void IOExpander::set_pwm_period(uint16_t value, bool load) {
|
2021-05-11 13:00:12 +01:00
|
|
|
value &= 0xffff;
|
|
|
|
i2c_reg_write_uint8(reg::PWMPL, (uint8_t)(value & 0xff));
|
|
|
|
i2c_reg_write_uint8(reg::PWMPH, (uint8_t)(value >> 8));
|
|
|
|
|
|
|
|
if(load)
|
|
|
|
pwm_load();
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
uint8_t IOExpander::get_mode(uint8_t pin) {
|
2021-05-11 13:00:12 +01:00
|
|
|
return pins[pin - 1].get_mode();
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
void IOExpander::set_mode(uint8_t pin, uint8_t mode, bool schmitt_trigger, bool invert) {
|
2021-05-11 13:00:12 +01:00
|
|
|
if(pin < 1 || pin > NUM_PINS)
|
|
|
|
{
|
|
|
|
printf("ValueError: Pin should be in range 1-14.\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
Pin& io_pin = pins[pin - 1];
|
|
|
|
|
|
|
|
uint8_t gpio_mode = mode & 0b11;
|
|
|
|
uint8_t io_type = (mode >> 2) & 0b11;
|
|
|
|
uint8_t initial_state = mode >> 4;
|
|
|
|
|
|
|
|
if(io_pin.get_mode() == mode) {
|
|
|
|
if(debug) {
|
|
|
|
printf("Mode already is %s\n", MODE_NAMES[io_type]);
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if((io_type != Pin::TYPE_IO) && !io_pin.mode_supported(mode)) {
|
|
|
|
if(debug) {
|
|
|
|
printf("Pin %d does not support %s!\n", pin, MODE_NAMES[io_type]);
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
io_pin.set_mode(mode);
|
|
|
|
if(debug) {
|
|
|
|
printf("Setting pin %d to mode %s %s, state: %s\n", pin, MODE_NAMES[io_type], GPIO_NAMES[gpio_mode], STATE_NAMES[initial_state]);
|
|
|
|
}
|
|
|
|
|
|
|
|
if(mode == PIN_MODE_PWM) {
|
|
|
|
set_bit(io_pin.reg_io_pwm, io_pin.pwm_channel);
|
|
|
|
change_bit(reg::PNP, io_pin.pwm_channel, invert);
|
|
|
|
set_bit(reg::PWMCON0, 7); //Set PWMRUN bit
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
if(io_pin.get_type() & Pin::TYPE_PWM)
|
|
|
|
clr_bit(io_pin.reg_io_pwm, io_pin.pwm_channel);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint8_t pm1 = i2c_reg_read_uint8(io_pin.reg_m1);
|
|
|
|
uint8_t pm2 = i2c_reg_read_uint8(io_pin.reg_m2);
|
|
|
|
|
|
|
|
//Clear the pm1 and pm2 bits
|
|
|
|
pm1 &= 255 - (1 << io_pin.pin);
|
|
|
|
pm2 &= 255 - (1 << io_pin.pin);
|
|
|
|
|
|
|
|
//Set the new pm1 and pm2 bits according to our gpio_mode
|
|
|
|
pm1 |= (gpio_mode >> 1) << io_pin.pin;
|
|
|
|
pm2 |= (gpio_mode & 0b1) << io_pin.pin;
|
|
|
|
|
|
|
|
i2c_reg_write_uint8(io_pin.reg_m1, pm1);
|
|
|
|
i2c_reg_write_uint8(io_pin.reg_m2, pm2);
|
|
|
|
|
|
|
|
//Set up Schmitt trigger mode on inputs
|
|
|
|
if(mode == PIN_MODE_PU || mode == PIN_MODE_IN)
|
|
|
|
change_bit(io_pin.reg_ps, io_pin.pin, schmitt_trigger);
|
|
|
|
|
|
|
|
//5th bit of mode encodes default output pin state
|
|
|
|
i2c_reg_write_uint8(io_pin.reg_p, (initial_state << 3) | io_pin.pin);
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
int16_t IOExpander::input(uint8_t pin, uint32_t adc_timeout) {
|
2021-05-11 13:00:12 +01:00
|
|
|
if(pin < 1 || pin > NUM_PINS)
|
|
|
|
{
|
|
|
|
if(debug)
|
|
|
|
printf("ValueError: Pin should be in range 1-14.\n");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
Pin& io_pin = pins[pin - 1];
|
|
|
|
|
|
|
|
if(io_pin.get_mode() == PIN_MODE_ADC) {
|
|
|
|
if(debug) {
|
|
|
|
printf("Reading ADC from pin %d\n", pin);
|
|
|
|
}
|
|
|
|
|
|
|
|
clr_bits(reg::ADCCON0, 0x0f);
|
|
|
|
set_bits(reg::ADCCON0, io_pin.adc_channel);
|
|
|
|
i2c_reg_write_uint8(reg::AINDIDS, 0);
|
|
|
|
set_bit(reg::AINDIDS, io_pin.adc_channel);
|
|
|
|
set_bit(reg::ADCCON1, 0);
|
|
|
|
|
|
|
|
clr_bit(reg::ADCCON0, 7); //ADCF - Clear the conversion complete flag
|
|
|
|
set_bit(reg::ADCCON0, 6); //ADCS - Set the ADC conversion start flag
|
|
|
|
|
|
|
|
//Wait for the ADCF conversion complete flag to be set
|
|
|
|
unsigned long start_time = millis();
|
|
|
|
while(!get_bit(reg::ADCCON0, 7)) {
|
|
|
|
sleep_ms(10);
|
|
|
|
if(millis() - start_time >= adc_timeout) {
|
|
|
|
if(debug)
|
|
|
|
printf("Timeout waiting for ADC conversion!");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
uint8_t hi = i2c_reg_read_uint8(reg::ADCRH);
|
|
|
|
uint8_t lo = i2c_reg_read_uint8(reg::ADCRL);
|
|
|
|
return (uint16_t)(hi << 4) | (uint16_t)lo;
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
if(debug) {
|
|
|
|
printf("Reading IO from pin %d\n", pin);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint8_t pv = get_bit(io_pin.reg_p, io_pin.pin);
|
|
|
|
return (pv) ? 1 : 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
float IOExpander::input_as_voltage(uint8_t pin, uint32_t adc_timeout) {
|
2021-05-11 13:00:12 +01:00
|
|
|
if(pin < 1 || pin > NUM_PINS)
|
|
|
|
{
|
|
|
|
if(debug)
|
|
|
|
printf("ValueError: Pin should be in range 1-14.\n");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
Pin& io_pin = pins[pin - 1];
|
|
|
|
|
|
|
|
if(io_pin.get_mode() == PIN_MODE_ADC) {
|
|
|
|
if(debug) {
|
|
|
|
printf("Reading ADC from pin %d\n", pin);
|
|
|
|
}
|
|
|
|
|
|
|
|
clr_bits(reg::ADCCON0, 0x0f);
|
|
|
|
set_bits(reg::ADCCON0, io_pin.adc_channel);
|
|
|
|
i2c_reg_write_uint8(reg::AINDIDS, 0);
|
|
|
|
set_bit(reg::AINDIDS, io_pin.adc_channel);
|
|
|
|
set_bit(reg::ADCCON1, 0);
|
|
|
|
|
|
|
|
|
|
|
|
clr_bit(reg::ADCCON0, 7); //ADCF - Clear the conversion complete flag
|
|
|
|
set_bit(reg::ADCCON0, 6); //ADCS - Set the ADC conversion start flag
|
|
|
|
|
|
|
|
//Wait for the ADCF conversion complete flag to be set
|
|
|
|
unsigned long start_time = millis();
|
|
|
|
while(!get_bit(reg::ADCCON0, 7)) {
|
|
|
|
sleep_ms(1);
|
|
|
|
if(millis() - start_time >= adc_timeout) {
|
|
|
|
if(debug)
|
|
|
|
printf("Timeout waiting for ADC conversion!\n");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
uint8_t hi = i2c_reg_read_uint8(reg::ADCRH);
|
|
|
|
uint8_t lo = i2c_reg_read_uint8(reg::ADCRL);
|
|
|
|
return ((float)((uint16_t)(hi << 4) | (uint16_t)lo) / 4095.0f) * vref;
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
if(debug) {
|
|
|
|
printf("Reading IO from pin %d\n", pin);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint8_t pv = get_bit(io_pin.reg_p, io_pin.pin);
|
|
|
|
return (pv) ? vref : 0.0f;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
void IOExpander::output(uint8_t pin, uint16_t value, bool load) {
|
2021-05-11 13:00:12 +01:00
|
|
|
if(pin < 1 || pin > NUM_PINS) {
|
|
|
|
printf("Pin should be in range 1-14.");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
Pin& io_pin = pins[pin - 1];
|
|
|
|
|
|
|
|
if(io_pin.get_mode() == PIN_MODE_PWM) {
|
|
|
|
if(debug) {
|
|
|
|
printf("Outputting PWM to pin: %d\n", pin);
|
|
|
|
}
|
|
|
|
|
|
|
|
i2c_reg_write_uint8(io_pin.reg_pwml, (uint8_t)(value & 0xff));
|
|
|
|
i2c_reg_write_uint8(io_pin.reg_pwmh, (uint8_t)(value >> 8));
|
|
|
|
if(load)
|
|
|
|
pwm_load();
|
|
|
|
}
|
|
|
|
else {
|
2021-05-11 17:18:43 +01:00
|
|
|
if(value == LOW) {
|
2021-05-11 13:00:12 +01:00
|
|
|
if(debug) {
|
|
|
|
printf("Outputting LOW to pin: %d\n", pin);
|
|
|
|
}
|
|
|
|
|
|
|
|
clr_bit(io_pin.reg_p, io_pin.pin);
|
|
|
|
}
|
2021-05-11 17:18:43 +01:00
|
|
|
else if(value == HIGH) {
|
2021-05-11 13:00:12 +01:00
|
|
|
if(debug) {
|
|
|
|
printf("Outputting HIGH to pin: %d\n", pin);
|
|
|
|
}
|
|
|
|
|
|
|
|
set_bit(io_pin.reg_p, io_pin.pin);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
void IOExpander::setup_rotary_encoder(uint8_t channel, uint8_t pinA, uint8_t pinB, uint8_t pinC, bool count_microsteps) {
|
2021-05-11 13:00:12 +01:00
|
|
|
channel -= 1;
|
|
|
|
set_mode(pinA, PIN_MODE_PU, true);
|
|
|
|
set_mode(pinB, PIN_MODE_PU, true);
|
|
|
|
|
|
|
|
if(pinC != 0) {
|
|
|
|
set_mode(pinC, PIN_MODE_OD);
|
|
|
|
output(pinC, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
i2c_reg_write_uint8(ENC_CFG[channel], pinA | (pinB << 4));
|
|
|
|
change_bit(reg::ENC_EN, (channel * 2) + 1, count_microsteps);
|
|
|
|
set_bit(reg::ENC_EN, channel * 2);
|
|
|
|
|
|
|
|
//Reset internal encoder count to zero
|
|
|
|
uint8_t reg = ENC_COUNT[channel];
|
|
|
|
i2c_reg_write_uint8(reg, 0x00);
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
int16_t IOExpander::read_rotary_encoder(uint8_t channel) {
|
2021-05-11 13:00:12 +01:00
|
|
|
channel -= 1;
|
|
|
|
int16_t last = encoder_last[channel];
|
|
|
|
uint8_t reg = ENC_COUNT[channel];
|
|
|
|
int16_t value = (int16_t)i2c_reg_read_uint8(reg);
|
|
|
|
|
|
|
|
if(value & 0b10000000)
|
|
|
|
value -= 256;
|
|
|
|
|
|
|
|
if(last > 64 && value < -64)
|
|
|
|
encoder_offset[channel] += 256;
|
|
|
|
if(last < -64 && value > 64)
|
|
|
|
encoder_offset[channel] -= 256;
|
|
|
|
|
|
|
|
encoder_last[channel] = value;
|
|
|
|
|
|
|
|
return encoder_offset[channel] + value;
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
uint8_t IOExpander::i2c_reg_read_uint8(uint8_t reg) {
|
2021-05-11 13:00:12 +01:00
|
|
|
uint8_t value;
|
|
|
|
i2c_write_blocking(i2c, address, ®, 1, true);
|
|
|
|
i2c_read_blocking(i2c, address, (uint8_t *)&value, 1, false);
|
|
|
|
return value;
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
void IOExpander::i2c_reg_write_uint8(uint8_t reg, uint8_t value) {
|
2021-05-11 13:00:12 +01:00
|
|
|
uint8_t buffer[2] = {reg, value};
|
|
|
|
i2c_write_blocking(i2c, address, buffer, 2, false);
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
uint8_t IOExpander::get_bit(uint8_t reg, uint8_t bit) {
|
2021-05-11 13:00:12 +01:00
|
|
|
//Returns the specified bit (nth position from right) from a register
|
|
|
|
return i2c_reg_read_uint8(reg) & (1 << bit);
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
void IOExpander::set_bits(uint8_t reg, uint8_t bits) {
|
2021-05-11 13:00:12 +01:00
|
|
|
//Set the specified bits (using a mask) in a register.
|
|
|
|
|
|
|
|
//Deal with special case registers first
|
|
|
|
bool reg_in_bit_addressed_regs = false;
|
|
|
|
for(uint8_t i = 0; i < NUM_BIT_ADDRESSED_REGISTERS; i++) {
|
|
|
|
if(BIT_ADDRESSED_REGS[i] == reg) {
|
|
|
|
for(uint8_t bit = 0; bit < 8; bit++) {
|
|
|
|
if(bits & (1 << bit))
|
|
|
|
i2c_reg_write_uint8(reg, 0b1000 | (bit & 0b111));
|
|
|
|
}
|
|
|
|
reg_in_bit_addressed_regs = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
//Now deal with any other registers
|
|
|
|
if(!reg_in_bit_addressed_regs) {
|
|
|
|
uint8_t value = i2c_reg_read_uint8(reg);
|
|
|
|
sleep_us(10);
|
|
|
|
i2c_reg_write_uint8(reg, value | bits);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
void IOExpander::set_bit(uint8_t reg, uint8_t bit) {
|
2021-05-11 13:00:12 +01:00
|
|
|
//Set the specified bit (nth position from right) in a register.
|
|
|
|
set_bits(reg, (1 << bit));
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
void IOExpander::clr_bits(uint8_t reg, uint8_t bits) {
|
2021-05-11 13:00:12 +01:00
|
|
|
bool reg_in_bit_addressed_regs = false;
|
|
|
|
for(uint8_t i = 0; i < NUM_BIT_ADDRESSED_REGISTERS; i++) {
|
|
|
|
if(BIT_ADDRESSED_REGS[i] == reg) {
|
|
|
|
for(uint8_t bit = 0; bit < 8; bit++) {
|
|
|
|
if(bits & (1 << bit))
|
|
|
|
i2c_reg_write_uint8(reg, 0b0000 | (bit & 0b111));
|
|
|
|
}
|
|
|
|
reg_in_bit_addressed_regs = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
//Now deal with any other registers
|
|
|
|
if(!reg_in_bit_addressed_regs) {
|
|
|
|
uint8_t value = i2c_reg_read_uint8(reg);
|
|
|
|
sleep_us(10);
|
|
|
|
i2c_reg_write_uint8(reg, value & ~bits);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
void IOExpander::clr_bit(uint8_t reg, uint8_t bit) {
|
2021-05-11 13:00:12 +01:00
|
|
|
//Clear the specified bit (nth position from right) in a register.
|
|
|
|
clr_bits(reg, (1 << bit));
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
void IOExpander::change_bit(uint8_t reg, uint8_t bit, bool state) {
|
2021-05-11 13:00:12 +01:00
|
|
|
//Toggle one register bit on/off.
|
|
|
|
if(state)
|
|
|
|
set_bit(reg, bit);
|
|
|
|
else
|
|
|
|
clr_bit(reg, bit);
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
void IOExpander::wait_for_flash(void) {
|
2021-05-11 13:00:12 +01:00
|
|
|
//Wait for the IOE to finish writing non-volatile memory.
|
|
|
|
unsigned long start_time = millis();
|
|
|
|
while(get_interrupt_flag()) {
|
|
|
|
if(millis() - start_time > timeout) {
|
|
|
|
printf("Timed out waiting for interrupt!\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
sleep_ms(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
start_time = millis();
|
|
|
|
while(!get_interrupt_flag()) {
|
|
|
|
if(millis() - start_time > timeout) {
|
|
|
|
printf("Timed out waiting for interrupt!\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
sleep_ms(1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-05-11 17:18:43 +01:00
|
|
|
uint32_t IOExpander::millis() {
|
2021-05-11 13:00:12 +01:00
|
|
|
return to_ms_since_boot(get_absolute_time());
|
|
|
|
}
|
|
|
|
}
|