2015-02-27 15:50:06 +00:00
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/*
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* This file is part of the Micro Python project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2015 Daniel Campora
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdint.h>
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#include <string.h>
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#include "py/mpstate.h"
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#include MICROPY_HAL_H
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2015-03-04 12:52:39 +00:00
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#include "py/runtime.h"
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#include "inc/hw_types.h"
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#include "inc/hw_ints.h"
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#include "inc/hw_nvic.h"
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#include "inc/hw_common_reg.h"
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#include "inc/hw_memmap.h"
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#include "cc3200_asm.h"
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#include "rom_map.h"
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#include "interrupt.h"
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#include "systick.h"
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#include "prcm.h"
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#include "spi.h"
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#include "pin.h"
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2015-02-27 15:50:06 +00:00
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#include "pybsleep.h"
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2015-03-04 12:52:39 +00:00
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#include "pybpin.h"
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#include "simplelink.h"
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2015-05-23 19:52:42 +01:00
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#include "modnetwork.h"
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2015-03-04 12:52:39 +00:00
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#include "modwlan.h"
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#include "osi.h"
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#include "debug.h"
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#include "mpexception.h"
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#include "mpcallback.h"
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#include "mperror.h"
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#include "sleeprestore.h"
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2015-05-22 18:53:33 +01:00
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#include "serverstask.h"
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2015-06-07 12:28:47 +01:00
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#include "antenna.h"
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2015-03-04 12:52:39 +00:00
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/******************************************************************************
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DECLARE PRIVATE CONSTANTS
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******************************************************************************/
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#define SPIFLASH_INSTR_READ_STATUS (0x05)
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#define SPIFLASH_INSTR_DEEP_POWER_DOWN (0xB9)
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#define SPIFLASH_STATUS_BUSY (0x01)
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2015-03-14 08:59:47 +00:00
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#define LPDS_UP_TIME (425) // 13 msec
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#define LPDS_DOWN_TIME (98) // 3 msec
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#define USER_OFFSET (131) // 4 smec
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#define WAKEUP_TIME_LPDS (LPDS_UP_TIME + LPDS_DOWN_TIME + USER_OFFSET) // 20 msec
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#define WAKEUP_TIME_HIB (32768) // 1 s
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2015-03-17 12:20:15 +00:00
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#define FORCED_TIMER_INTERRUPT_MS (1)
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#define FAILED_SLEEP_DELAY_MS (FORCED_TIMER_INTERRUPT_MS * 3)
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2015-03-04 12:52:39 +00:00
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/******************************************************************************
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DECLARE PRIVATE TYPES
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******************************************************************************/
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// storage memory for Cortex M4 registers
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2015-02-27 15:50:06 +00:00
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typedef struct {
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uint32_t msp;
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uint32_t psp;
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uint32_t psr;
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uint32_t primask;
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uint32_t faultmask;
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uint32_t basepri;
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uint32_t control;
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2015-03-04 12:52:39 +00:00
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} arm_cm4_core_regs_t;
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2015-02-27 15:50:06 +00:00
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2015-03-04 12:52:39 +00:00
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// storage memory for the NVIC registers
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typedef struct {
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uint32_t vector_table; // Vector Table Offset
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uint32_t aux_ctrl; // Auxiliary control register
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uint32_t int_ctrl_state; // Interrupt Control and State
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uint32_t app_int; // Application Interrupt Reset control
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uint32_t sys_ctrl; // System control
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uint32_t config_ctrl; // Configuration control
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uint32_t sys_pri_1; // System Handler Priority 1
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uint32_t sys_pri_2; // System Handler Priority 2
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uint32_t sys_pri_3; // System Handler Priority 3
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uint32_t sys_hcrs; // System Handler control and state register
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uint32_t systick_ctrl; // SysTick Control Status
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uint32_t systick_reload; // SysTick Reload
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uint32_t systick_calib; // SysTick Calibration
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uint32_t int_en[6]; // Interrupt set enable
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uint32_t int_priority[49]; // Interrupt priority
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} nvic_reg_store_t;
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2015-02-27 15:50:06 +00:00
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2015-03-04 12:52:39 +00:00
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typedef struct {
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mp_obj_base_t base;
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mp_obj_t obj;
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WakeUpCB_t wakeup;
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} pybsleep_obj_t;
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2015-02-27 15:50:06 +00:00
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2015-03-04 12:52:39 +00:00
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typedef struct {
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2015-03-14 08:59:47 +00:00
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mp_obj_t wlan_lpds_wake_cb;
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mp_obj_t timer_lpds_wake_cb;
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mp_obj_t gpio_lpds_wake_cb;
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2015-03-17 12:20:15 +00:00
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uint timer_wake_pwrmode;
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2015-03-26 13:27:21 +00:00
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} pybsleep_data_t;
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2015-03-04 12:52:39 +00:00
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/******************************************************************************
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DECLARE PRIVATE DATA
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******************************************************************************/
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STATIC const mp_obj_type_t pybsleep_type;
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STATIC nvic_reg_store_t *nvic_reg_store;
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2015-03-26 13:27:21 +00:00
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STATIC pybsleep_data_t pybsleep_data = {NULL, NULL, NULL, 0};
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2015-03-04 12:52:39 +00:00
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volatile arm_cm4_core_regs_t vault_arm_registers;
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2015-03-14 08:59:47 +00:00
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STATIC pybsleep_reset_cause_t pybsleep_reset_cause = PYB_SLP_PWRON_RESET;
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2015-05-29 13:52:56 +01:00
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STATIC pybsleep_wake_reason_t pybsleep_wake_reason = PYB_SLP_WAKED_PWRON;
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2015-03-04 12:52:39 +00:00
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/******************************************************************************
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DECLARE PRIVATE FUNCTIONS
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******************************************************************************/
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STATIC pybsleep_obj_t *pybsleep_find (mp_obj_t obj);
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STATIC void pybsleep_flash_powerdown (void);
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STATIC NORETURN void pybsleep_suspend_enter (void);
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void pybsleep_suspend_exit (void);
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STATIC void pybsleep_obj_wakeup (void);
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STATIC void PRCMInterruptHandler (void);
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2015-06-06 17:42:51 +01:00
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STATIC void pybsleep_iopark (bool hibernate);
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2015-03-17 12:20:15 +00:00
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STATIC bool setup_timer_lpds_wake (void);
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STATIC bool setup_timer_hibernate_wake (void);
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2015-03-04 12:52:39 +00:00
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/******************************************************************************
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DEFINE PUBLIC FUNCTIONS
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******************************************************************************/
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2015-03-14 08:59:47 +00:00
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__attribute__ ((section (".boot")))
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void pybsleep_pre_init (void) {
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2015-03-04 12:52:39 +00:00
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// allocate memory for nvic registers vault
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ASSERT ((nvic_reg_store = mem_Malloc(sizeof(nvic_reg_store_t))) != NULL);
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2015-03-14 08:59:47 +00:00
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}
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void pybsleep_init0 (void) {
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// initialize the sleep objects list
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mp_obj_list_init(&MP_STATE_PORT(pybsleep_obj_list), 0);
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2015-02-27 15:50:06 +00:00
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2015-03-14 08:59:47 +00:00
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// register and enable the PRCM interrupt
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2015-03-04 12:52:39 +00:00
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osi_InterruptRegister(INT_PRCM, (P_OSI_INTR_ENTRY)PRCMInterruptHandler, INT_PRIORITY_LVL_1);
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2015-03-14 08:59:47 +00:00
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2015-03-15 23:40:59 +00:00
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// disable all LPDS and hibernate wake up sources (WLAN is disabed/enabled before entering LDPS mode)
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MAP_PRCMLPDSWakeupSourceDisable(PRCM_LPDS_GPIO);
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MAP_PRCMLPDSWakeupSourceDisable(PRCM_LPDS_TIMER);
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2015-03-17 12:20:15 +00:00
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MAP_PRCMHibernateWakeupSourceDisable(PRCM_HIB_SLOW_CLK_CTR | PRCM_HIB_GPIO2 | PRCM_HIB_GPIO4 | PRCM_HIB_GPIO13 |
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PRCM_HIB_GPIO17 | PRCM_HIB_GPIO11 | PRCM_HIB_GPIO24 | PRCM_HIB_GPIO26);
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2015-03-15 23:40:59 +00:00
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2015-03-14 08:59:47 +00:00
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// store the reset casue (if it's soft reset, leave it as it is)
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if (pybsleep_reset_cause != PYB_SLP_SOFT_RESET) {
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switch (MAP_PRCMSysResetCauseGet()) {
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case PRCM_POWER_ON:
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pybsleep_reset_cause = PYB_SLP_PWRON_RESET;
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break;
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case PRCM_CORE_RESET:
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case PRCM_MCU_RESET:
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case PRCM_SOC_RESET:
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pybsleep_reset_cause = PYB_SLP_HARD_RESET;
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break;
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case PRCM_WDT_RESET:
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pybsleep_reset_cause = PYB_SLP_WDT_RESET;
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break;
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case PRCM_HIB_EXIT:
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if (PRCMWasResetBecauseOfWDT()) {
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pybsleep_reset_cause = PYB_SLP_WDT_RESET;
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}
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else {
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pybsleep_reset_cause = PYB_SLP_HIB_RESET;
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2015-05-01 22:09:29 +01:00
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// set the correct wake reason
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switch (MAP_PRCMHibernateWakeupCauseGet()) {
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case PRCM_HIB_WAKEUP_CAUSE_SLOW_CLOCK:
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pybsleep_wake_reason = PYB_SLP_WAKED_BY_RTC;
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break;
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case PRCM_HIB_WAKEUP_CAUSE_GPIO:
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pybsleep_wake_reason = PYB_SLP_WAKED_BY_GPIO;
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break;
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default:
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break;
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}
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2015-03-14 08:59:47 +00:00
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}
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break;
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default:
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break;
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}
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}
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}
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void pybsleep_signal_soft_reset (void) {
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pybsleep_reset_cause = PYB_SLP_SOFT_RESET;
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2015-02-27 15:50:06 +00:00
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}
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2015-03-04 12:52:39 +00:00
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void pybsleep_add (const mp_obj_t obj, WakeUpCB_t wakeup) {
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pybsleep_obj_t * sleep_obj = m_new_obj(pybsleep_obj_t);
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sleep_obj->base.type = &pybsleep_type;
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sleep_obj->obj = obj;
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sleep_obj->wakeup = wakeup;
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// only add objects once
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if (!pybsleep_find(sleep_obj)) {
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mp_obj_list_append(&MP_STATE_PORT(pybsleep_obj_list), sleep_obj);
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}
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2015-02-27 15:50:06 +00:00
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}
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2015-03-04 12:52:39 +00:00
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void pybsleep_remove (const mp_obj_t obj) {
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pybsleep_obj_t *sleep_obj;
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if ((sleep_obj = pybsleep_find(obj))) {
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mp_obj_list_remove(&MP_STATE_PORT(pybsleep_obj_list), sleep_obj);
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}
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2015-02-27 15:50:06 +00:00
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}
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2015-03-12 15:14:55 +00:00
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void pybsleep_set_wlan_lpds_callback (mp_obj_t cb_obj) {
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2015-03-26 13:27:21 +00:00
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pybsleep_data.wlan_lpds_wake_cb = cb_obj;
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2015-03-04 12:52:39 +00:00
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}
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2015-02-27 15:50:06 +00:00
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2015-03-12 15:14:55 +00:00
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void pybsleep_set_gpio_lpds_callback (mp_obj_t cb_obj) {
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2015-03-26 13:27:21 +00:00
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pybsleep_data.gpio_lpds_wake_cb = cb_obj;
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2015-03-04 12:52:39 +00:00
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}
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2015-02-27 15:50:06 +00:00
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2015-03-12 15:14:55 +00:00
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void pybsleep_set_timer_lpds_callback (mp_obj_t cb_obj) {
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2015-03-26 13:27:21 +00:00
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pybsleep_data.timer_lpds_wake_cb = cb_obj;
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2015-03-04 12:52:39 +00:00
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}
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2015-02-27 15:50:06 +00:00
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2015-03-17 12:20:15 +00:00
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void pybsleep_configure_timer_wakeup (uint pwrmode) {
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2015-03-26 13:27:21 +00:00
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pybsleep_data.timer_wake_pwrmode = pwrmode;
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2015-03-17 12:20:15 +00:00
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}
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2015-03-20 12:39:43 +00:00
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pybsleep_reset_cause_t pybsleep_get_reset_cause (void) {
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return pybsleep_reset_cause;
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}
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2015-03-04 12:52:39 +00:00
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/******************************************************************************
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DEFINE PRIVATE FUNCTIONS
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******************************************************************************/
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STATIC pybsleep_obj_t *pybsleep_find (mp_obj_t obj) {
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for (mp_uint_t i = 0; i < MP_STATE_PORT(pybsleep_obj_list).len; i++) {
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// search for the object and then remove it
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pybsleep_obj_t *sleep_obj = ((pybsleep_obj_t *)(MP_STATE_PORT(pybsleep_obj_list).items[i]));
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if (sleep_obj->obj == obj) {
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return sleep_obj;
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2015-02-27 15:50:06 +00:00
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}
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2015-03-04 12:52:39 +00:00
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}
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return NULL;
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2015-02-27 15:50:06 +00:00
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}
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2015-03-04 12:52:39 +00:00
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STATIC void pybsleep_flash_powerdown (void) {
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2015-02-27 15:50:06 +00:00
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uint32_t status;
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// Enable clock for SSPI module
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2015-03-04 12:52:39 +00:00
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MAP_PRCMPeripheralClkEnable(PRCM_SSPI, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
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2015-02-27 15:50:06 +00:00
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// Reset SSPI at PRCM level and wait for reset to complete
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MAP_PRCMPeripheralReset(PRCM_SSPI);
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2015-03-04 12:52:39 +00:00
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while(!MAP_PRCMPeripheralStatusGet(PRCM_SSPI));
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2015-02-27 15:50:06 +00:00
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// Reset SSPI at module level
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MAP_SPIReset(SSPI_BASE);
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// Configure SSPI module
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MAP_SPIConfigSetExpClk (SSPI_BASE, PRCMPeripheralClockGet(PRCM_SSPI),
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20000000, SPI_MODE_MASTER,SPI_SUB_MODE_0,
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(SPI_SW_CTRL_CS |
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SPI_4PIN_MODE |
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SPI_TURBO_OFF |
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SPI_CS_ACTIVELOW |
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SPI_WL_8));
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// Enable SSPI module
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MAP_SPIEnable(SSPI_BASE);
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// Enable chip select for the spi flash.
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MAP_SPICSEnable(SSPI_BASE);
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// Wait for the spi flash
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do {
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// Send the status register read instruction and read back a dummy byte.
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2015-03-04 12:52:39 +00:00
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MAP_SPIDataPut(SSPI_BASE, SPIFLASH_INSTR_READ_STATUS);
|
2015-02-27 15:50:06 +00:00
|
|
|
MAP_SPIDataGet(SSPI_BASE, &status);
|
|
|
|
|
|
|
|
// Write a dummy byte then read back the actual status.
|
|
|
|
MAP_SPIDataPut(SSPI_BASE, 0xFF);
|
|
|
|
MAP_SPIDataGet(SSPI_BASE, &status);
|
2015-03-04 12:52:39 +00:00
|
|
|
} while ((status & 0xFF) == SPIFLASH_STATUS_BUSY);
|
2015-02-27 15:50:06 +00:00
|
|
|
|
|
|
|
// Disable chip select for the spi flash.
|
|
|
|
MAP_SPICSDisable(SSPI_BASE);
|
|
|
|
// Start another CS enable sequence for Power down command.
|
|
|
|
MAP_SPICSEnable(SSPI_BASE);
|
|
|
|
// Send Deep Power Down command to spi flash
|
2015-03-04 12:52:39 +00:00
|
|
|
MAP_SPIDataPut(SSPI_BASE, SPIFLASH_INSTR_DEEP_POWER_DOWN);
|
2015-02-27 15:50:06 +00:00
|
|
|
// Disable chip select for the spi flash.
|
|
|
|
MAP_SPICSDisable(SSPI_BASE);
|
|
|
|
}
|
|
|
|
|
2015-03-04 12:52:39 +00:00
|
|
|
STATIC NORETURN void pybsleep_suspend_enter (void) {
|
|
|
|
// enable full RAM retention
|
|
|
|
MAP_PRCMSRAMRetentionEnable(PRCM_SRAM_COL_1 | PRCM_SRAM_COL_2 | PRCM_SRAM_COL_3 | PRCM_SRAM_COL_4, PRCM_SRAM_LPDS_RET);
|
|
|
|
|
|
|
|
// save the NVIC control registers
|
|
|
|
nvic_reg_store->vector_table = HWREG(NVIC_VTABLE);
|
|
|
|
nvic_reg_store->aux_ctrl = HWREG(NVIC_ACTLR);
|
|
|
|
nvic_reg_store->int_ctrl_state = HWREG(NVIC_INT_CTRL);
|
|
|
|
nvic_reg_store->app_int = HWREG(NVIC_APINT);
|
|
|
|
nvic_reg_store->sys_ctrl = HWREG(NVIC_SYS_CTRL);
|
|
|
|
nvic_reg_store->config_ctrl = HWREG(NVIC_CFG_CTRL);
|
|
|
|
nvic_reg_store->sys_pri_1 = HWREG(NVIC_SYS_PRI1);
|
|
|
|
nvic_reg_store->sys_pri_2 = HWREG(NVIC_SYS_PRI2);
|
|
|
|
nvic_reg_store->sys_pri_3 = HWREG(NVIC_SYS_PRI3);
|
|
|
|
nvic_reg_store->sys_hcrs = HWREG(NVIC_SYS_HND_CTRL);
|
|
|
|
|
|
|
|
// save the systick registers
|
|
|
|
nvic_reg_store->systick_ctrl = HWREG(NVIC_ST_CTRL);
|
|
|
|
nvic_reg_store->systick_reload = HWREG(NVIC_ST_RELOAD);
|
|
|
|
nvic_reg_store->systick_calib = HWREG(NVIC_ST_CAL);
|
|
|
|
|
|
|
|
// save the interrupt enable registers
|
|
|
|
uint32_t *base_reg_addr = (uint32_t *)NVIC_EN0;
|
|
|
|
for(int32_t i = 0; i < (sizeof(nvic_reg_store->int_en) / 4); i++) {
|
|
|
|
nvic_reg_store->int_en[i] = base_reg_addr[i];
|
|
|
|
}
|
2015-02-27 15:50:06 +00:00
|
|
|
|
2015-03-04 12:52:39 +00:00
|
|
|
// save the interrupt priority registers
|
|
|
|
base_reg_addr = (uint32_t *)NVIC_PRI0;
|
|
|
|
for(int32_t i = 0; i < (sizeof(nvic_reg_store->int_priority) / 4); i++) {
|
|
|
|
nvic_reg_store->int_priority[i] = base_reg_addr[i];
|
|
|
|
}
|
2015-02-27 15:50:06 +00:00
|
|
|
|
2015-03-26 12:51:37 +00:00
|
|
|
// switch off the heartbeat led (this makes sure it will blink as soon as we wake up)
|
|
|
|
mperror_heartbeat_switch_off();
|
|
|
|
|
2015-03-11 15:50:13 +00:00
|
|
|
// park the gpio pins
|
2015-06-06 17:42:51 +01:00
|
|
|
pybsleep_iopark(false);
|
2015-03-04 12:52:39 +00:00
|
|
|
|
2015-03-11 15:50:13 +00:00
|
|
|
// store the cpu registers
|
2015-03-04 12:52:39 +00:00
|
|
|
sleep_store();
|
|
|
|
|
|
|
|
// save the restore info and enter LPDS
|
|
|
|
MAP_PRCMLPDSRestoreInfoSet(vault_arm_registers.psp, (uint32_t)sleep_restore);
|
|
|
|
MAP_PRCMLPDSEnter();
|
|
|
|
|
|
|
|
// let the cpu fade away...
|
|
|
|
for ( ; ; );
|
|
|
|
}
|
|
|
|
|
|
|
|
void pybsleep_suspend_exit (void) {
|
|
|
|
// take the I2C semaphore
|
|
|
|
uint32_t reg = HWREG(COMMON_REG_BASE + COMMON_REG_O_I2C_Properties_Register);
|
|
|
|
reg = (reg & ~0x3) | 0x1;
|
|
|
|
HWREG(COMMON_REG_BASE + COMMON_REG_O_I2C_Properties_Register) = reg;
|
|
|
|
|
|
|
|
// take the GPIO semaphore
|
|
|
|
reg = HWREG(COMMON_REG_BASE + COMMON_REG_O_GPIO_properties_register);
|
|
|
|
reg = (reg & ~0x3FF) | 0x155;
|
|
|
|
HWREG(COMMON_REG_BASE + COMMON_REG_O_GPIO_properties_register) = reg;
|
|
|
|
|
|
|
|
// restore de NVIC control registers
|
|
|
|
HWREG(NVIC_VTABLE) = nvic_reg_store->vector_table;
|
|
|
|
HWREG(NVIC_ACTLR) = nvic_reg_store->aux_ctrl;
|
|
|
|
HWREG(NVIC_INT_CTRL) = nvic_reg_store->int_ctrl_state;
|
|
|
|
HWREG(NVIC_APINT) = nvic_reg_store->app_int;
|
|
|
|
HWREG(NVIC_SYS_CTRL) = nvic_reg_store->sys_ctrl;
|
|
|
|
HWREG(NVIC_CFG_CTRL) = nvic_reg_store->config_ctrl;
|
|
|
|
HWREG(NVIC_SYS_PRI1) = nvic_reg_store->sys_pri_1;
|
|
|
|
HWREG(NVIC_SYS_PRI2) = nvic_reg_store->sys_pri_2;
|
|
|
|
HWREG(NVIC_SYS_PRI3) = nvic_reg_store->sys_pri_3;
|
|
|
|
HWREG(NVIC_SYS_HND_CTRL) = nvic_reg_store->sys_hcrs;
|
|
|
|
|
|
|
|
// restore the systick register
|
|
|
|
HWREG(NVIC_ST_CTRL) = nvic_reg_store->systick_ctrl;
|
|
|
|
HWREG(NVIC_ST_RELOAD) = nvic_reg_store->systick_reload;
|
|
|
|
HWREG(NVIC_ST_CAL) = nvic_reg_store->systick_calib;
|
|
|
|
|
|
|
|
// restore the interrupt priority registers
|
|
|
|
uint32_t *base_reg_addr = (uint32_t *)NVIC_PRI0;
|
|
|
|
for (uint32_t i = 0; i < (sizeof(nvic_reg_store->int_priority) / 4); i++) {
|
|
|
|
base_reg_addr[i] = nvic_reg_store->int_priority[i];
|
|
|
|
}
|
2015-02-27 15:50:06 +00:00
|
|
|
|
2015-03-04 12:52:39 +00:00
|
|
|
// restore the interrupt enable registers
|
|
|
|
base_reg_addr = (uint32_t *)NVIC_EN0;
|
|
|
|
for(uint32_t i = 0; i < (sizeof(nvic_reg_store->int_en) / 4); i++) {
|
|
|
|
base_reg_addr[i] = nvic_reg_store->int_en[i];
|
|
|
|
}
|
2015-02-27 15:50:06 +00:00
|
|
|
|
2015-03-04 12:52:39 +00:00
|
|
|
HAL_INTRODUCE_SYNC_BARRIER();
|
2015-02-27 15:50:06 +00:00
|
|
|
|
2015-03-04 12:52:39 +00:00
|
|
|
// ungate the clock to the shared spi bus
|
|
|
|
MAP_PRCMPeripheralClkEnable(PRCM_SSPI, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
|
2015-02-27 15:50:06 +00:00
|
|
|
|
2015-06-08 09:35:23 +01:00
|
|
|
#if MICROPY_HW_ANTENNA_DIVERSITY
|
2015-06-07 12:28:47 +01:00
|
|
|
// re-configure the antenna selection pins
|
|
|
|
antenna_init0();
|
2015-06-08 09:35:23 +01:00
|
|
|
#endif
|
2015-06-07 12:28:47 +01:00
|
|
|
|
2015-03-26 12:51:37 +00:00
|
|
|
// reinitialize simplelink's interface
|
2015-03-12 09:35:38 +00:00
|
|
|
sl_IfOpen (NULL, 0);
|
2015-02-27 15:50:06 +00:00
|
|
|
|
2015-03-04 12:52:39 +00:00
|
|
|
// restore the configuration of all active peripherals
|
|
|
|
pybsleep_obj_wakeup();
|
2015-02-27 15:50:06 +00:00
|
|
|
|
2015-03-26 12:51:37 +00:00
|
|
|
// reconfigure all the previously enabled interrupts
|
|
|
|
mpcallback_wake_all();
|
|
|
|
|
2015-03-04 12:52:39 +00:00
|
|
|
// trigger a sw interrupt
|
|
|
|
MAP_IntPendSet(INT_PRCM);
|
2015-02-27 15:50:06 +00:00
|
|
|
|
2015-03-04 12:52:39 +00:00
|
|
|
// force an exception to go back to the point where suspend mode was entered
|
|
|
|
nlr_raise(mp_obj_new_exception(&mp_type_SystemExit));
|
2015-02-27 15:50:06 +00:00
|
|
|
}
|
|
|
|
|
2015-03-04 12:52:39 +00:00
|
|
|
STATIC void PRCMInterruptHandler (void) {
|
|
|
|
// reading the interrupt status automatically clears the interrupt
|
|
|
|
if (PRCM_INT_SLOW_CLK_CTR == MAP_PRCMIntStatus()) {
|
2015-03-14 08:59:47 +00:00
|
|
|
// this interrupt is triggered during active mode
|
2015-03-26 13:27:21 +00:00
|
|
|
mpcallback_handler(pybsleep_data.timer_lpds_wake_cb);
|
2015-03-04 12:52:39 +00:00
|
|
|
}
|
|
|
|
else {
|
2015-03-14 08:59:47 +00:00
|
|
|
// interrupt has been triggered while waking up from LPDS
|
2015-03-04 12:52:39 +00:00
|
|
|
switch (MAP_PRCMLPDSWakeupCauseGet()) {
|
2015-02-27 15:50:06 +00:00
|
|
|
case PRCM_LPDS_HOST_IRQ:
|
2015-03-26 13:27:21 +00:00
|
|
|
mpcallback_handler(pybsleep_data.wlan_lpds_wake_cb);
|
2015-05-01 22:09:29 +01:00
|
|
|
pybsleep_wake_reason = PYB_SLP_WAKED_BY_WLAN;
|
2015-03-04 12:52:39 +00:00
|
|
|
break;
|
2015-02-27 15:50:06 +00:00
|
|
|
case PRCM_LPDS_GPIO:
|
2015-03-26 13:27:21 +00:00
|
|
|
mpcallback_handler(pybsleep_data.gpio_lpds_wake_cb);
|
2015-05-01 22:09:29 +01:00
|
|
|
pybsleep_wake_reason = PYB_SLP_WAKED_BY_GPIO;
|
2015-03-04 12:52:39 +00:00
|
|
|
break;
|
2015-02-27 15:50:06 +00:00
|
|
|
case PRCM_LPDS_TIMER:
|
2015-05-22 18:53:33 +01:00
|
|
|
// disable the timer as wake-up source
|
2015-03-26 13:27:21 +00:00
|
|
|
pybsleep_data.timer_wake_pwrmode &= ~PYB_PWR_MODE_LPDS;
|
2015-03-17 12:20:15 +00:00
|
|
|
MAP_PRCMLPDSWakeupSourceDisable(PRCM_LPDS_TIMER);
|
2015-03-26 13:27:21 +00:00
|
|
|
mpcallback_handler(pybsleep_data.timer_lpds_wake_cb);
|
2015-05-01 22:09:29 +01:00
|
|
|
pybsleep_wake_reason = PYB_SLP_WAKED_BY_RTC;
|
2015-03-04 12:52:39 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
2015-02-27 15:50:06 +00:00
|
|
|
}
|
2015-03-04 12:52:39 +00:00
|
|
|
}
|
2015-02-27 15:50:06 +00:00
|
|
|
}
|
|
|
|
|
2015-03-04 12:52:39 +00:00
|
|
|
STATIC void pybsleep_obj_wakeup (void) {
|
|
|
|
for (mp_uint_t i = 0; i < MP_STATE_PORT(pybsleep_obj_list).len; i++) {
|
|
|
|
pybsleep_obj_t *sleep_obj = ((pybsleep_obj_t *)MP_STATE_PORT(pybsleep_obj_list).items[i]);
|
|
|
|
sleep_obj->wakeup(sleep_obj->obj);
|
|
|
|
}
|
2015-02-27 15:50:06 +00:00
|
|
|
}
|
|
|
|
|
2015-06-06 17:42:51 +01:00
|
|
|
STATIC void pybsleep_iopark (bool hibernate) {
|
2015-03-04 12:52:39 +00:00
|
|
|
mp_map_t *named_map = mp_obj_dict_get_map((mp_obj_t)&pin_cpu_pins_locals_dict);
|
|
|
|
for (uint i = 0; i < named_map->used; i++) {
|
|
|
|
pin_obj_t * pin = (pin_obj_t *)named_map->table[i].value;
|
|
|
|
// skip the sflash pins since these are shared with the network processor
|
|
|
|
switch (pin->pin_num) {
|
|
|
|
#ifdef DEBUG
|
2015-06-06 17:42:51 +01:00
|
|
|
// skip the JTAG pins
|
2015-03-04 12:52:39 +00:00
|
|
|
case PIN_16:
|
|
|
|
case PIN_17:
|
|
|
|
case PIN_19:
|
|
|
|
case PIN_20:
|
|
|
|
break;
|
2015-06-06 17:42:51 +01:00
|
|
|
#endif
|
2015-03-04 12:52:39 +00:00
|
|
|
default:
|
2015-03-26 12:51:37 +00:00
|
|
|
// enable a weak pull-down if the pin is unused
|
|
|
|
if (!pin->isused) {
|
2015-03-04 12:52:39 +00:00
|
|
|
MAP_PinConfigSet(pin->pin_num, pin->strength, PIN_TYPE_STD_PD);
|
|
|
|
}
|
2015-06-06 17:42:51 +01:00
|
|
|
if (hibernate) {
|
|
|
|
// make it an input
|
|
|
|
MAP_PinDirModeSet(pin->pin_num, PIN_DIR_MODE_IN);
|
|
|
|
}
|
2015-03-04 12:52:39 +00:00
|
|
|
break;
|
2015-02-27 15:50:06 +00:00
|
|
|
}
|
2015-03-04 12:52:39 +00:00
|
|
|
}
|
2015-02-27 15:50:06 +00:00
|
|
|
|
2015-03-04 12:52:39 +00:00
|
|
|
// park the sflash pins
|
|
|
|
HWREG(0x4402E0E8) &= ~(0x3 << 8);
|
|
|
|
HWREG(0x4402E0E8) |= (0x2 << 8);
|
|
|
|
HWREG(0x4402E0EC) &= ~(0x3 << 8);
|
|
|
|
HWREG(0x4402E0EC) |= (0x2 << 8);
|
|
|
|
HWREG(0x4402E0F0) &= ~(0x3 << 8);
|
|
|
|
HWREG(0x4402E0F0) |= (0x2 << 8);
|
|
|
|
HWREG(0x4402E0F4) &= ~(0x3 << 8);
|
|
|
|
HWREG(0x4402E0F4) |= (0x1 << 8);
|
|
|
|
|
2015-06-06 17:42:51 +01:00
|
|
|
// if the board has antenna diversity, only park the antenna
|
|
|
|
// selection pins when going into hibernation
|
|
|
|
#if MICROPY_HW_ANTENNA_DIVERSITY
|
|
|
|
if (hibernate) {
|
|
|
|
#endif
|
|
|
|
// park the antenna selection pins
|
2015-06-10 11:41:29 +01:00
|
|
|
// (tri-stated with pull down enabled)
|
2015-06-06 17:42:51 +01:00
|
|
|
HWREG(0x4402E108) = 0x00000E61;
|
|
|
|
HWREG(0x4402E10C) = 0x00000E61;
|
|
|
|
#if MICROPY_HW_ANTENNA_DIVERSITY
|
2015-06-10 11:41:29 +01:00
|
|
|
} else {
|
|
|
|
// park the antenna selection pins
|
|
|
|
// (tri-stated without changing the pull up/down resistors)
|
|
|
|
HWREG(0x4402E108) &= ~0x000000FF;
|
|
|
|
HWREG(0x4402E108) |= 0x00000C61;
|
|
|
|
HWREG(0x4402E10C) &= ~0x000000FF;
|
|
|
|
HWREG(0x4402E10C) |= 0x00000C61;
|
2015-06-06 17:42:51 +01:00
|
|
|
}
|
|
|
|
#endif
|
2015-03-04 12:52:39 +00:00
|
|
|
}
|
|
|
|
|
2015-03-17 12:20:15 +00:00
|
|
|
STATIC bool setup_timer_lpds_wake (void) {
|
|
|
|
uint64_t t_match, t_curr, t_remaining;
|
|
|
|
|
|
|
|
// get the time remaining for the RTC timer to expire
|
|
|
|
t_match = MAP_PRCMSlowClkCtrMatchGet();
|
|
|
|
t_curr = MAP_PRCMSlowClkCtrGet();
|
|
|
|
|
|
|
|
if (t_match > t_curr) {
|
|
|
|
// get the time remaining in terms of slow clocks
|
|
|
|
t_remaining = (t_match - t_curr);
|
|
|
|
if (t_remaining > WAKEUP_TIME_LPDS) {
|
|
|
|
// subtract the time it takes for wakeup from lpds
|
|
|
|
t_remaining -= WAKEUP_TIME_LPDS;
|
|
|
|
t_remaining = (t_remaining > 0xFFFFFFFF) ? 0xFFFFFFFF: t_remaining;
|
|
|
|
// setup the LPDS wake time
|
|
|
|
MAP_PRCMLPDSIntervalSet((uint32_t)t_remaining);
|
|
|
|
// enable the wake source
|
|
|
|
MAP_PRCMLPDSWakeupSourceEnable(PRCM_LPDS_TIMER);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
// setup a timer interrupt immediately
|
|
|
|
MAP_PRCMRTCMatchSet(0, FORCED_TIMER_INTERRUPT_MS);
|
|
|
|
}
|
|
|
|
|
|
|
|
// disable the timer as wake source
|
|
|
|
MAP_PRCMLPDSWakeupSourceDisable(PRCM_LPDS_TIMER);
|
|
|
|
|
|
|
|
// LPDS wake by timer was not possible, force
|
|
|
|
// an interrupt in active mode instead
|
|
|
|
MAP_PRCMIntEnable(PRCM_INT_SLOW_CLK_CTR);
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
STATIC bool setup_timer_hibernate_wake (void) {
|
|
|
|
uint64_t t_match, t_curr, t_remaining;
|
|
|
|
|
|
|
|
// get the time remaining for the RTC timer to expire
|
|
|
|
t_match = MAP_PRCMSlowClkCtrMatchGet();
|
|
|
|
t_curr = MAP_PRCMSlowClkCtrGet();
|
|
|
|
|
|
|
|
if (t_match > t_curr) {
|
|
|
|
// get the time remaining in terms of slow clocks
|
|
|
|
t_remaining = (t_match - t_curr);
|
|
|
|
if (t_remaining > WAKEUP_TIME_HIB) {
|
|
|
|
// subtract the time it takes for wakeup from hibernate
|
|
|
|
t_remaining -= WAKEUP_TIME_HIB;
|
|
|
|
// setup the LPDS wake time
|
|
|
|
MAP_PRCMHibernateIntervalSet((uint32_t)t_remaining);
|
|
|
|
// enable the wake source
|
|
|
|
MAP_PRCMHibernateWakeupSourceEnable(PRCM_HIB_SLOW_CLK_CTR);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
// setup a timer interrupt immediately
|
|
|
|
MAP_PRCMRTCMatchSet(0, FORCED_TIMER_INTERRUPT_MS);
|
|
|
|
}
|
|
|
|
|
|
|
|
// disable the timer as wake source
|
|
|
|
MAP_PRCMLPDSWakeupSourceDisable(PRCM_HIB_SLOW_CLK_CTR);
|
|
|
|
|
|
|
|
// hibernate wake by timer was not possible, force
|
|
|
|
// an interrupt in active mode instead
|
|
|
|
MAP_PRCMIntEnable(PRCM_INT_SLOW_CLK_CTR);
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2015-03-04 12:52:39 +00:00
|
|
|
/******************************************************************************/
|
|
|
|
// Micro Python bindings; Sleep class
|
|
|
|
|
|
|
|
/// \function idle()
|
|
|
|
/// Gates the processor clock until an interrupt is triggered
|
|
|
|
STATIC mp_obj_t pyb_sleep_idle (mp_obj_t self_in) {
|
|
|
|
__WFI();
|
|
|
|
return mp_const_none;
|
|
|
|
}
|
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_sleep_idle_obj, pyb_sleep_idle);
|
|
|
|
|
2015-03-12 09:35:38 +00:00
|
|
|
/// \function suspend(wlan)
|
2015-03-04 12:52:39 +00:00
|
|
|
/// Enters suspended mode. Wake up sources should have been enable prior to
|
2015-03-12 09:35:38 +00:00
|
|
|
/// calling this method.
|
2015-03-04 12:52:39 +00:00
|
|
|
STATIC mp_obj_t pyb_sleep_suspend (mp_obj_t self_in) {
|
|
|
|
nlr_buf_t nlr;
|
2015-03-11 15:50:13 +00:00
|
|
|
|
2015-03-17 12:20:15 +00:00
|
|
|
// check if we should enable timer wake-up
|
2015-03-26 13:27:21 +00:00
|
|
|
if (pybsleep_data.timer_wake_pwrmode & PYB_PWR_MODE_LPDS) {
|
2015-03-17 12:20:15 +00:00
|
|
|
if (!setup_timer_lpds_wake()) {
|
|
|
|
// lpds entering is not possible, wait for the forced interrupt and return
|
2015-03-26 13:27:21 +00:00
|
|
|
pybsleep_data.timer_wake_pwrmode &= ~PYB_PWR_MODE_LPDS;
|
2015-03-17 12:20:15 +00:00
|
|
|
HAL_Delay (FAILED_SLEEP_DELAY_MS);
|
|
|
|
return mp_const_none;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-03-26 13:27:21 +00:00
|
|
|
// do we need network wake-up?
|
|
|
|
if (pybsleep_data.wlan_lpds_wake_cb) {
|
2015-03-11 15:50:13 +00:00
|
|
|
MAP_PRCMLPDSWakeupSourceEnable (PRCM_LPDS_HOST_IRQ);
|
2015-05-22 18:53:33 +01:00
|
|
|
server_sleep_sockets();
|
2015-03-11 15:50:13 +00:00
|
|
|
}
|
|
|
|
else {
|
|
|
|
MAP_PRCMLPDSWakeupSourceDisable (PRCM_LPDS_HOST_IRQ);
|
|
|
|
}
|
2015-03-04 12:52:39 +00:00
|
|
|
|
2015-03-26 13:27:21 +00:00
|
|
|
// entering and exiting suspended mode must be an atomic operation
|
2015-03-12 09:35:38 +00:00
|
|
|
// therefore interrupts need to be disabled
|
2015-03-04 12:52:39 +00:00
|
|
|
uint primsk = disable_irq();
|
|
|
|
if (nlr_push(&nlr) == 0) {
|
|
|
|
pybsleep_suspend_enter();
|
|
|
|
nlr_pop();
|
|
|
|
}
|
2015-03-17 12:20:15 +00:00
|
|
|
|
2015-03-04 12:52:39 +00:00
|
|
|
// an exception is always raised when exiting suspend mode
|
|
|
|
enable_irq(primsk);
|
2015-02-27 15:50:06 +00:00
|
|
|
|
2015-03-04 12:52:39 +00:00
|
|
|
return mp_const_none;
|
2015-02-27 15:50:06 +00:00
|
|
|
}
|
2015-03-04 12:52:39 +00:00
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_sleep_suspend_obj, pyb_sleep_suspend);
|
2015-02-27 15:50:06 +00:00
|
|
|
|
2015-03-04 12:52:39 +00:00
|
|
|
/// \function hibernate()
|
|
|
|
/// Enters hibernate mode. Wake up sources should have been enable prior to
|
2015-03-14 08:59:47 +00:00
|
|
|
/// calling this method.
|
2015-03-04 12:52:39 +00:00
|
|
|
STATIC mp_obj_t pyb_sleep_hibernate (mp_obj_t self_in) {
|
2015-03-17 12:20:15 +00:00
|
|
|
// check if we should enable timer wake-up
|
2015-03-26 13:27:21 +00:00
|
|
|
if (pybsleep_data.timer_wake_pwrmode & PYB_PWR_MODE_HIBERNATE) {
|
2015-03-17 12:20:15 +00:00
|
|
|
if (!setup_timer_hibernate_wake()) {
|
|
|
|
// hibernating is not possible, wait for the forced interrupt and return
|
2015-03-26 13:27:21 +00:00
|
|
|
pybsleep_data.timer_wake_pwrmode &= ~PYB_PWR_MODE_HIBERNATE;
|
2015-03-17 12:20:15 +00:00
|
|
|
HAL_Delay (FAILED_SLEEP_DELAY_MS);
|
|
|
|
return mp_const_none;
|
|
|
|
}
|
|
|
|
}
|
2015-03-18 20:49:48 +00:00
|
|
|
wlan_stop(SL_STOP_TIMEOUT);
|
2015-03-04 12:52:39 +00:00
|
|
|
pybsleep_flash_powerdown();
|
2015-03-26 12:51:37 +00:00
|
|
|
// must be done just before entering hibernate mode
|
2015-06-06 17:42:51 +01:00
|
|
|
pybsleep_iopark(true);
|
2015-03-04 12:52:39 +00:00
|
|
|
MAP_PRCMHibernateEnter();
|
|
|
|
return mp_const_none;
|
2015-02-27 15:50:06 +00:00
|
|
|
}
|
2015-03-04 12:52:39 +00:00
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_sleep_hibernate_obj, pyb_sleep_hibernate);
|
2015-02-27 15:50:06 +00:00
|
|
|
|
2015-03-14 08:59:47 +00:00
|
|
|
/// \function reset_cause()
|
|
|
|
/// Returns the last reset casue
|
|
|
|
STATIC mp_obj_t pyb_sleep_reset_cause (mp_obj_t self_in) {
|
|
|
|
return MP_OBJ_NEW_SMALL_INT(pybsleep_reset_cause);
|
|
|
|
}
|
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_sleep_reset_cause_obj, pyb_sleep_reset_cause);
|
|
|
|
|
|
|
|
/// \function wake_reason()
|
|
|
|
/// Returns the wake up reson from ldps or hibernate
|
|
|
|
STATIC mp_obj_t pyb_sleep_wake_reason (mp_obj_t self_in) {
|
2015-05-01 22:09:29 +01:00
|
|
|
return MP_OBJ_NEW_SMALL_INT(pybsleep_wake_reason);
|
2015-03-14 08:59:47 +00:00
|
|
|
}
|
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_sleep_wake_reason_obj, pyb_sleep_wake_reason);
|
|
|
|
|
2015-03-04 12:52:39 +00:00
|
|
|
STATIC const mp_map_elem_t pybsleep_locals_dict_table[] = {
|
|
|
|
// instance methods
|
|
|
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_idle), (mp_obj_t)&pyb_sleep_idle_obj },
|
|
|
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_suspend), (mp_obj_t)&pyb_sleep_suspend_obj },
|
|
|
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_hibernate), (mp_obj_t)&pyb_sleep_hibernate_obj },
|
2015-03-14 08:59:47 +00:00
|
|
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_reset_cause), (mp_obj_t)&pyb_sleep_reset_cause_obj },
|
|
|
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_wake_reason), (mp_obj_t)&pyb_sleep_wake_reason_obj },
|
2015-02-27 15:50:06 +00:00
|
|
|
|
2015-03-04 12:52:39 +00:00
|
|
|
// class constants
|
2015-03-12 15:14:55 +00:00
|
|
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_ACTIVE), MP_OBJ_NEW_SMALL_INT(PYB_PWR_MODE_ACTIVE) },
|
2015-03-04 12:52:39 +00:00
|
|
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_SUSPENDED), MP_OBJ_NEW_SMALL_INT(PYB_PWR_MODE_LPDS) },
|
|
|
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_HIBERNATING), MP_OBJ_NEW_SMALL_INT(PYB_PWR_MODE_HIBERNATE) },
|
2015-05-01 22:09:29 +01:00
|
|
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_POWER_ON), MP_OBJ_NEW_SMALL_INT(PYB_SLP_PWRON_RESET) },
|
2015-03-14 08:59:47 +00:00
|
|
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_HARD_RESET), MP_OBJ_NEW_SMALL_INT(PYB_SLP_HARD_RESET) },
|
|
|
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_WDT_RESET), MP_OBJ_NEW_SMALL_INT(PYB_SLP_WDT_RESET) },
|
|
|
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_HIB_RESET), MP_OBJ_NEW_SMALL_INT(PYB_SLP_HIB_RESET) },
|
|
|
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_SOFT_RESET), MP_OBJ_NEW_SMALL_INT(PYB_SLP_SOFT_RESET) },
|
|
|
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_WLAN_WAKE), MP_OBJ_NEW_SMALL_INT(PYB_SLP_WAKED_BY_WLAN) },
|
2015-05-01 22:09:29 +01:00
|
|
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_PIN_WAKE), MP_OBJ_NEW_SMALL_INT(PYB_SLP_WAKED_BY_GPIO) },
|
2015-03-14 08:59:47 +00:00
|
|
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_WAKE), MP_OBJ_NEW_SMALL_INT(PYB_SLP_WAKED_BY_RTC) },
|
2015-03-04 12:52:39 +00:00
|
|
|
};
|
2015-02-27 15:50:06 +00:00
|
|
|
|
2015-03-04 12:52:39 +00:00
|
|
|
STATIC MP_DEFINE_CONST_DICT(pybsleep_locals_dict, pybsleep_locals_dict_table);
|
2015-02-27 15:50:06 +00:00
|
|
|
|
2015-03-04 12:52:39 +00:00
|
|
|
STATIC const mp_obj_type_t pybsleep_type = {
|
|
|
|
{ &mp_type_type },
|
2015-04-29 14:23:22 +01:00
|
|
|
.name = MP_QSTR_Sleep,
|
2015-03-04 12:52:39 +00:00
|
|
|
.locals_dict = (mp_obj_t)&pybsleep_locals_dict,
|
|
|
|
};
|
2015-02-27 15:50:06 +00:00
|
|
|
|
2015-03-04 12:52:39 +00:00
|
|
|
const mp_obj_base_t pyb_sleep_obj = {&pybsleep_type};
|