The board.json file is intentionally excluded, until the board will be
sold. But including it into the mimxrt series make it easier to keep
the build up-to-date.
- Manufacturer, set by MICROPY_HW_USB_STR_MANUF; default "MicroPython"
- Board name, as set by MICROPY_HW_BOARD_NAME
- Unique-ID, same as returned by machine.unique_id()
- USB Vendor ID, as set by MICROPY_HW_USB_VID; default 0xf055
- USB Product ID, as set by MICROPY_HW_USB_PID; default 0x9802
Using the keyword argument cs=nnn in the constructor. The cs1
pin has to be defined in mpconfigboard.h.
Note: Only a few boards have the CS1 pin exposed to the connectors.
The Pin config setting by IOMUXC_SetPinConfig() is supplied by a
bit pattern. That pattern is specific for a MCU family. In preparation
for supporting the MIMXRT117x family, the constant bit pattern is
replaced by a function call, such that the bit pattern is created
at a single place. The code for this functions was taken from
machine_pin.c.
Note: A working port for the MIMXRT1176 exists already.
This library file has a bug, in that TransferBlocking returns before the
transfer has finished. That is a problem if a write follows immediately
a read.
If in a board's mkconfigboard.mk the following symbol is set:
MICROPY_HW_BOARD_FLASH_FILES = 1
then the files:
($BOARD)_flexspi_flash_config.h and
qspi_nor_flash_config.c and/or
qspi_hyper_flash_config.c
are expected in the board directory. Otherwise the common files from
the hal directory are used.
This is needed because these ports allocate mbedtls data on the MicroPython
heap, and SSL socket objects must be fully cleaned up when they are garbage
collected, to free this memory allocated by mbedtls. As part of this,
gc_sweep_all() will now ensure that the MP_STATE_PORT(mbedtls_memory)
linked-list is fully deallocated on soft reset.
Signed-off-by: Damien George <damien@micropython.org>
If MICROPY_PY_SYS_PATH_ARGV_DEFAULTS is enabled (which it is by default)
then sys.path and sys.argv will be initialised and populated with default
values. This keeps all bare-metal ports aligned.
Signed-off-by: Damien George <damien@micropython.org>
Frozen modules will be searched preferentially, but gives the user the
ability to override this behavior.
This matches the previous behavior where "" was implicitly the frozen
search path, but the frozen list was checked before the filesystem.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
- Move the qspi_xxxx_flash_config.c files to hal.
It turned out that they are less board than flash type specific.
- Change to a common flexspi_flash_config.h header file.
Thanks for the hint, Damien. The DEBUG build got very large recently.
The major difference is, that inline function are now inlined and
not included as a function. That's good and maybe bad. The good thing is,
that the code speed si now close to the final code. It could be worse
in single step debugging. I'll see.
Setting this option caused a new warning and a formatting error
to pop up at different places. Fixed as well.
The ID is read in a single function and used for:
- machine.unique_id()
- Ethernet MAC addresses.
- ...
That facilitates use of other MCU using a different access method for
the ID (e.g. i.MX RT1176).
Just another choice for the PHY interface.
Added: Keyword option phy_clock=LAN.IN or LAN.OUT
to define the source of the 50MHZ clock for the PHY
interface. The RMII clock is not enabled if it
is generated by a PYH board. Constants:
LAN.IN The clock is provided by the PHY board.
LAN.OUT The clock is provided by the MCU board.
The default is LAN.OUT or the value set in mpconfigboard.h, which
is currently set to IN only for the SEEED ARCH MIX board. Usage etc:
lan = LAN(phy_type=LAN.PHY_DP83848, phy_clock=LAN.IN)
The initial problem with a wrong ICMP checksum was caused by
the test code setting a checksum and the HW taking that probably as
the start value and ending up with 0xffff. With a checksum field of 0
set by the test code the HW creates the proper checksum.
Useful for boards without a PHY interface, where that has to be
attached. Like the Seed ARCH MIX board or Vision SOM. Phy drivers
supported so far are:
- KSZ8081
- DP83825
- LAN8720
More to come. Usage e.g.:
lan = LAN(phy_type=LAN.PHY_LAN8720, phy_addr=1)
The default values are those set in mpconfigboard.h.
UART 0 is attached to the Debug USB port. The settings are
115200 Baud, 8N1.
For MIMXRT1010_EVK this is identical to UART1. For the other boards,
this is an additional UART.
Frequency range 15Hz/18Hz to > 1 MHz, with decreasing resolution of the
duty cycle. The basic API is supported as documentated, except that
keyword parameters are accepted for both the instatiaton and the
PWM.init() call.
Extensions: support PWM for channel pairs. Channel pairs are declared by
supplying 2-element tuples for the pins. The two channels of a pair must
be the A/B channel of a FLEXPWM module. These form than a complementary
pair.
Additional supported keyword arguments:
- center=value Defines the center position of a pulse within the pulse
cycle. The align keyword is actually shortcut for center.
- sync=True|False: If set to True, the channels will be synchronized to a
submodule 0 channel, which has already to be enabled.
- align=PWM.MIDDLE | PMW.BEGIN | PWM.END. It defines, whether synchronized
channels are Center-Aligned or Edge-aligned. The channels must be either
complementary a channel pair or a group of synchronized channels. It may
as well be applied to a single channel, but withiout any benefit.
- invert= 0..3. Controls ouput inversion of the pins. Bit 0 controls the
first pin, bit 1 the second.
- deadtime=time_ns time of complementary channels for delaying the rising
slope.
- xor=0|1|2 xor causes the output of channel A and B to be xored. If
applied to a X channel, it shows the value oif A ^ B. If applied to an A
or B channel, both channel show the xored signal for xor=1. For xor=2,
the xored signal is split between channels A and B. See also the
Reference Manual, chapter about double pulses. The behavior of xor=2 can
also be achieved using the center method for locating a pulse within a
clock period.
The output is enabled for board pins only.
CPU pins may still be used for FLEXPWM, e.g. as sync source, but the signal
will not be routed to the output. That applies only to FLEXPWM pins. The
use of QTMR pins which are not board pins will be rejected.
As part of this commit, the _WFE() statement is removed from
ticks_delay_us64() to prevent PWM glitching during calls to sleep().
- Add board.md files for MIMXRT1060_EVK and MIMXRT1064_EVK warning about
their experimental state.
- Add separate deploy_teensy.md and deploy_mimxrt.md files.
The ARCH MIX board exposes the Ethernet Pins at it's connectors. Therefore
the software is configured for using a LAN8720 PHY device. Breakout boards
with the LAN8720 are easily available.
This will be used by https://micropython.org/download/ to generate the
full listing of boards and firmware files.
Optionally supports a board.md for additional customisation of the
download page, as well as deploy.md for flashing instructions.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
By moving code to ITCM, like vm, gc, parse, runtime. The change affects
mostly the execution speed of MicroPython code. The speed is increased by
up to a factor of 6, especially for MCU with small cache.
Prior to this commit mp_hal_ticks_cpu() was not started properly. It only
started when the code was executed with a debugger attached, except for the
Teensy (i.MXRT1062) boards. As an additional fix, the CYYCNT timer is now
started at boot time.
Also rename mp_hal_ticks_cpu_init() to mp_hal_ticks_cpu_enable().
The API follows that of rp2, stm32, esp32, and the docs.
wdt=machine.WDT(0, timeout)
Timeout is given in ms. The valid range is 500 to 128000 (128
seconds) with 500 ms granularity. Values outside of that range will
be silently aligned.
wdt.feed()
Resets the watchdog timer (feeding).
wdt.timeout_ms(value)
Sets a new timeout and feeds the watchdog.
This is a new, preliminary method which is not yet documented.
reset_cause = machine.reset_cause()
Values returned:
1 Power On reset
3 Watchdog reset
5 Software reset: state after calling machine.reset()
More elaborate API functions are supported by the MCU, like an interrupt
called a certain time after feeding. But for port cosistency that is not
implemented.
This commit implements 10/100 Mbit Ethernet support in the mimxrt port.
The following boards are configured without ETH network:
- MIMXRT1010_EVK
- Teensy 4.0
The following boards are configured with ETH network:
- MIMXRT1020_EVK
- MIMXRT1050_EVK
- MIMXRT1060_EVK
- MIMXRT1064_EVK
- Teensy 4.1
Ethernet support tested with TEENSY 4.1, MIMRTX1020_EVK and MIMXRT1050_EVK.
Build tested with Teensy 4.0 and MIMXRT1010_EVK to be still working.
Compiles and builds properly for MIMXRT1060_EVK and MIMXRT1064_EVK, but not
tested lacking suitable boards.
Tested functions are:
- ping works bothway
- simple UDP transfer works bothway
- ntptime works
- the ftp server works
- secure socker works
- telnet and webrepl works
The MAC address is 0x02 plus 5 bytes from the manifacturing info field,
which can be considered as unique per device.
Some boards do not wire the RESET and INT pin of the PHY transceiver. For
operation, these are not required. If they are defined, they will be used.
Adds support for SDRAM via `SEMC` peripheral. SDRAM support can be
enabled in the mpconfigboard.mk file by setting `MICROPY_HW_SDRAM_AVAIL`
to `1` and poviding the size of the RAM via `MICROPY_HW_FLASH_SIZE`.
When SDRAM support is enabled the whole SDRAM is currently used used
for MicroPython heap.
Signed-off-by: Philipp Ebensberger
- Moves definition of BOARD_FLASH_SIZE and other header files related to
flash configuration into the Makefile.
- Adds board specific clock_config.h.
- Adds board.h, pin_mux.h, and peripherals.h as they are
required by NXP MCU SDK in order to use our own clock_config.h.
- Renames board specific FlexSPI configuration files.
- Updates flash frequency of MIMXRT1020_EVK
- Creates separated flash_config files for QSPI NOR and
QSPI Hyper flash.
- Unifies VFS start address to be @ 1M for 1010 and 1020 boards.
- Unifies 1050EVK boards
- Adds support to both NOR and HyperFlash on boards with
both capabilities.
- Adds automatic FlexRAM initialization to start-up code based on
linker script and NXP HAL.
- Applies code formatting to all files in mimxrt port.
With this change the flash configuration is restructured and
organized. This simplifies the configuration process and
provides a better overview of each board's settings. With the integration
of clock_config.h, board.h, pin_mux.h, and peripherals.h we gain better
control of the settings and clock configurations. Furthermore the
implementation of an explicit FlexRAM setup improves the system
performance and allows for performance tuning.
Signed-off-by: Philipp Ebensberger
Following the code example for ESP32 of Jim Mussard.
As a side effect:
- mp_hal_ticks_cpu() was implemented,
- mp_hal_get_cpu_freq() and mp_hal_ticks_cpu_init() were added and used.
- mp_hal_pin_high() and mp_hal_pin_low() were changed for symmetry
- Configures `PLL2->PFD0` with **198MHz** as base clock of
`USDHCx` peripheral.
- Adds guards for SDCard related files via `MICROPY_PY_MACHINE_SDCARD`
- Adds creation of pin defines for SDCard to make-pins.py
- Adds new configuration option for SDCard peripheral pinout
to mpconfigport.h
- Adds interrupt handling support instead of polling
- Adds support for `ADMA2` powered data transfer
- Configures SDCard to run in HS (high-speed mode) with **50MHz** only!
SDCard support is optional and requires `USDHC` peripheral.
Thus this driver is not available on `MIMXRT1010_EVK`.
SDCard support is enabled by setting `MICROPY_PY_MACHINE_SDCARD = 1`
in mpconfigboard.mk.
Signed-off-by: Philipp Ebensberger
The zephyr port doesn't support SoftI2C so it's not enabled, and the legacy
I2C constructor check can be removed.
Signed-off-by: Damien George <damien@micropython.org>
For consistency with other board-level config macros that begin with
MICROPY_HW_USB.
Also allow boards in the mimxrt, nrf and samd ports to configure these
values.
Signed-off-by: Damien George <damien@micropython.org>
robert-hh
Damien George
Chris Boudacoff
Jim Mussared
Mike Causer
Philipp Ebensberger