micropython/ports/stm32/boards/stm32h573_af.csv

15 KiB

1PortAF0AF1AF2AF3AF4AF5AF6AF7AF8AF9AF10AF11AF12AF13AF14AF15
2SYSLPTIM1/TIM1/2/16/17LPTIM3/PDM_SAI1/TIM3/4/5/12/15I3C1/LPTIM2/3/LPUART1/OCTOSPI/TIM1/8CEC/DCMI/I2C1/2/3/4/LPTIM1/2/SPI1/I2S1/TIM15/USART1CEC/I3C1/LPTIM1/SPI1/I2S1/SPI2/I2S2/SPI3/I2S3/SPI4/5/6I2C4/OCTOSPI/SAI1/SPI3/I2S3/SPI4/UART4/12/USART10/USB_PDSDMMC1/SPI2/I2S2/SPI3/I2S3/SPI6/UART7/8/12/USART1/2/3/6/10/11LPUART1/SAI2/SDMMC1/SPI6/UART4/5/8FDCAN1/2/FMC[NAND16]/FMC[NORmux]/FMC[NOR_RAM]/OCTOSPI/SDMMC2/TIM13/14CRS/FMC[NAND16]/OCTOSPI/SAI2/SDMMC2/TIM8/USB_ETH[MII/RMII]/FMC[NAND16]/OCTOSPI/SDMMC2/UART7/9/USB_PDFMC[NAND16]/FMC[NORmux]/FMC[NOR_RAM]/FMC[SDRAM_16bit]/SDMMC1DCMI/FMC[NAND16]/FMC[NORmux]/FMC[NOR_RAM]/LPTIM5LPTIM3/4/5/6/TIM2/UART5SYSADC
3PortAPA0TIM2_CH1TIM5_CH1TIM8_ETRTIM15_BKINSPI6_NSSSPI3_RDYUSART2_CTS/USART2_NSSUART4_TXSDMMC2_CMDSAI2_SD_BETH_MII_CRSTIM2_ETREVENTOUTADC12_INP0/ADC12_INN1
4PortAPA1TIM2_CH2TIM5_CH2TIM15_CH1NLPTIM1_IN1OCTOSPI1_DQSUSART2_RTSUART4_RXOCTOSPI1_IO3SAI2_MCLK_BETH_MII_RX_CLK/ETH_RMII_REF_CLKEVENTOUTADC12_INP1
5PortAPA2TIM2_CH3TIM5_CH3TIM15_CH1LPTIM1_IN2USART2_TXSAI2_SCK_BETH_MDIOEVENTOUTADC12_INP14
6PortAPA3TIM2_CH4TIM5_CH4OCTOSPI1_CLKTIM15_CH2SPI2_NSS/I2S2_WSSAI1_SD_BUSART2_RXETH_MII_COLEVENTOUTADC12_INP15
7PortAPA4TIM5_ETRLPTIM2_CH1SPI1_NSS/I2S1_WSSPI3_NSS/I2S3_WSUSART2_CKSPI6_NSSDCMI_HSYNC/PSSI_DEEVENTOUTADC12_INP18
8PortAPA5TIM2_CH1TIM8_CH1NSPI1_SCK/I2S1_CKSPI6_SCKETH_MII_TX_EN/ETH_RMII_TX_ENPSSI_D14TIM2_ETREVENTOUTADC12_INP19/ADC12_INN18
9PortAPA6TIM1_BKINTIM3_CH1TIM8_BKINSPI1_MISO/I2S1_SDIOCTOSPI1_IO3USART11_TXSPI6_MISOTIM13_CH1DCMI_PIXCLK/PSSI_PDCKEVENTOUTADC12_INP3
10PortAPA7TIM1_CH1NTIM3_CH2TIM8_CH1NSPI1_MOSI/I2S1_SDOUSART11_RXSPI6_MOSITIM14_CH1OCTOSPI1_IO2ETH_MII_RX_DV/ETH_RMII_CRS_DVFMC_SDNWEFMC_NWEEVENTOUTADC12_INP7/ADC12_INN3
11PortAPA8MCO1TIM1_CH1TIM8_BKIN2I2C3_SCLSPI1_RDYUSART1_CKUSB_SOFUART7_RXFMC_NOEDCMI_D3/PSSI_D3EVENTOUT
12PortAPA9TIM1_CH2LPUART1_TXI2C3_SMBASPI2_SCK/I2S2_CKUSART1_TXETH_MII_TX_ERFMC_NWEDCMI_D0/PSSI_D0EVENTOUT
13PortAPA10TIM1_CH3LPUART1_RXLPTIM2_IN2UCPD1_FRSTXUSART1_RXFDCAN2_TXSDMMC1_D0DCMI_D1/PSSI_D1EVENTOUT
14PortAPA11TIM1_CH4LPUART1_CTSSPI2_NSS/I2S2_WSUART4_RXUSART1_CTS/USART1_NSSFDCAN1_RXUSB_DMEVENTOUT
15PortAPA12TIM1_ETRLPUART1_RTSSPI2_SCK/I2S2_CKUART4_TXUSART1_RTSSAI2_FS_BFDCAN1_TXUSB_DPEVENTOUT
16PortAPA13JTMS/SWDIOEVENTOUT
17PortAPA14JTCK/SWCLKEVENTOUT
18PortAPA15JTDITIM2_CH1LPTIM3_IN2HDMI_CECSPI1_NSS/I2S1_WSSPI3_NSS/I2S3_WSSPI6_NSSUART4_RTSUART7_TXFMC_NBL1DCMI_D11/PSSI_D11TIM2_ETREVENTOUT
19PortBPB0TIM1_CH2NTIM3_CH3TIM8_CH2NOCTOSPI1_IO1USART11_CKUART4_CTSETH_MII_RXD2LPTIM3_CH1EVENTOUTADC12_INP9/ADC12_INN5
20PortBPB1TIM1_CH3NTIM3_CH4TIM8_CH3NOCTOSPI1_IO0ETH_MII_RXD3LPTIM3_CH2EVENTOUTADC12_INP5
21PortBPB2RTC_OUT2SAI1_D1TIM8_CH4NSPI1_RDYLPTIM1_CH1SAI1_SD_ASPI3_MOSI/I2S3_SDOOCTOSPI1_CLKOCTOSPI1_DQSSDMMC1_CMDLPTIM5_ETREVENTOUT
22PortBPB3JTDO/TRACESWOTIM2_CH2I2C2_SDASPI1_SCK/I2S1_CKSPI3_SCK/I2S3_CKUART12_CTS/UART12_NSSSPI6_SCKSDMMC2_D2CRS_SYNCUART7_RXLPTIM6_ETREVENTOUT
23PortBPB4NJTRSTTIM16_BKINTIM3_CH1OCTOSPI1_CLKLPTIM1_CH2SPI1_MISO/I2S1_SDISPI3_MISO/I2S3_SDISPI2_NSS/I2S2_WSSPI6_MISOSDMMC2_D3UART7_TXDCMI_D7/PSSI_D7EVENTOUT
24PortBPB5TIM17_BKINTIM3_CH2OCTOSPI1_NCLKI2C1_SMBASPI1_MOSI/I2S1_SDOI2C4_SMBASPI3_MOSI/I2S3_SDOSPI6_MOSIFDCAN2_RXETH_PPS_OUTFMC_SDCKE1DCMI_D10/PSSI_D10UART5_RXEVENTOUT
25PortBPB6TIM16_CH1NTIM4_CH1I3C1_SCLI2C1_SCLHDMI_CECI2C4_SCLUSART1_TXLPUART1_TXFDCAN2_TXOCTOSPI1_NCSFMC_SDNE1DCMI_D5/PSSI_D5UART5_TXEVENTOUT
26PortBPB7TIM17_CH1NTIM4_CH2I3C1_SDAI2C1_SDAI2C4_SDAUSART1_RXLPUART1_RXFDCAN1_TXSDMMC2_D5SDMMC2_CKINFMC_NLDCMI_VSYNC/PSSI_RDYEVENTOUT
27PortBPB8TIM16_CH1TIM4_CH3I3C1_SCLI2C1_SCLSPI4_RDYI2C4_SCLSDMMC1_CKINUART4_RXFDCAN1_RXSDMMC2_D4ETH_MII_TXD3SDMMC1_D4DCMI_D6/PSSI_D6EVENTOUT
28PortBPB9TIM17_CH1TIM4_CH4I3C1_SDAI2C1_SDASPI2_NSS/I2S2_WSI2C4_SDASDMMC1_CDIRUART4_TXFDCAN1_TXSDMMC2_D5SDMMC2_CKINSDMMC1_D5DCMI_D7/PSSI_D7EVENTOUT
29PortBPB10TIM2_CH3LPTIM3_CH1LPTIM2_IN1I2C2_SCLSPI2_SCK/I2S2_CKUSART3_TXOCTOSPI1_NCSETH_MII_RX_EREVENTOUT
30PortBPB11TIM2_CH4LPTIM2_ETRI2C2_SDASPI2_RDYSPI4_RDYUSART3_RXETH_MII_TX_EN/ETH_RMII_TX_ENFMC_NBL1EVENTOUT
31PortBPB12TIM1_BKINOCTOSPI1_NCLKI2C2_SDASPI2_NSS/I2S2_WSUCPD1_FRSTXUSART3_CKFDCAN2_RXETH_MII_TXD0/ETH_RMII_TXD0UART5_RXEVENTOUT
32PortBPB13TIM1_CH1NLPTIM3_IN1LPTIM2_CH1I2C2_SMBASPI2_SCK/I2S2_CKUSART3_CTS/USART3_NSSFDCAN2_TXSDMMC1_D0UART5_TXEVENTOUT
33PortBPB14TIM1_CH2NTIM12_CH1TIM8_CH2NUSART1_TXSPI2_MISO/I2S2_SDIUSART3_RTSUART4_RTSSDMMC2_D0LPTIM3_ETREVENTOUT
34PortBPB15RTC_REFINTIM1_CH3NTIM12_CH2TIM8_CH3NUSART1_RXSPI2_MOSI/I2S2_SDOUSART11_CTS/USART11_NSSUART4_CTSSDMMC2_D1OCTOSPI1_CLKETH_MII_TXD1/ETH_RMII_TXD1DCMI_D2/PSSI_D2UART5_RXEVENTOUT
35PortCPC0TIM16_BKINSAI1_MCLK_ASPI2_RDYSAI2_FS_BFMC_A25OCTOSPI1_IO7FMC_SDNWEEVENTOUTADC12_INP10
36PortCPC1TRACED0SAI1_D1SPI2_MOSI/I2S2_SDOSAI1_SD_AUSART11_RTSSAI2_SD_ASDMMC2_CKOCTOSPI1_IO4ETH_MDCEVENTOUTADC12_INP11/ADC12_INN10
37PortCPC2PWR_CSLEEPTIM17_CH1TIM4_CH4SPI2_MISO/I2S2_SDIOCTOSPI1_IO5OCTOSPI1_IO2ETH_MII_TXD2FMC_SDNE0EVENTOUTADC12_INP12/ADC12_INN11
38PortCPC3PWR_CSTOPSAI1_D3LPTIM3_CH1SPI2_MOSI/I2S2_SDOOCTOSPI1_IO6OCTOSPI1_IO0ETH_MII_TX_CLKFMC_SDCKE0EVENTOUTADC12_INP13/ADC12_INN12
39PortCPC4TIM2_CH4SAI1_CK1LPTIM2_ETRI2S1_MCKUSART3_RXETH_MII_RXD0/ETH_RMII_RXD0FMC_SDNE0EVENTOUTADC12_INP4
40PortCPC5TIM1_CH4NSAI1_D3PSSI_D15SAI1_FS_AUART12_RTSOCTOSPI1_DQSETH_MII_RXD1/ETH_RMII_RXD1FMC_SDCKE0EVENTOUTADC12_INP8/ADC12_INN4
41PortCPC6TIM3_CH1TIM8_CH1I2S2_MCKSAI1_SCK_AUSART6_TXSDMMC1_D0DIRFMC_NWAITSDMMC2_D6OCTOSPI1_IO5SDMMC1_D6DCMI_D0/PSSI_D0EVENTOUT
42PortCPC7TRGIOTIM3_CH2TIM8_CH2I2S3_MCKUSART6_RXSDMMC1_D123DIRFMC_NE1SDMMC2_D7OCTOSPI1_IO6SDMMC1_D7DCMI_D1/PSSI_D1EVENTOUT
43PortCPC8TRACED1TIM3_CH3TIM8_CH3USART6_CKUART5_RTSFMC_NE2/FMC_NCEFMC_INTFMC_ALESDMMC1_D0DCMI_D2/PSSI_D2EVENTOUT
44PortCPC9MCO2TIM3_CH4TIM8_CH4I2C3_SDAAUDIOCLKUART5_CTSOCTOSPI1_IO0FMC_CLESDMMC1_D1DCMI_D3/PSSI_D3EVENTOUT
45PortCPC10LPTIM3_ETRSPI3_SCK/I2S3_CKUSART3_TXUART4_TXOCTOSPI1_IO1ETH_MII_TXD0/ETH_RMII_TXD0SDMMC1_D2DCMI_D8/PSSI_D8EVENTOUT
46PortCPC11LPTIM3_IN1SPI3_MISO/I2S3_SDIUSART3_RXUART4_RXOCTOSPI1_NCSSDMMC1_D3DCMI_D4/PSSI_D4EVENTOUT
47PortCPC12TRACED3TIM15_CH1SPI6_SCKSPI3_MOSI/I2S3_SDOUSART3_CKUART5_TXSDMMC1_CKDCMI_D9/PSSI_D9EVENTOUT
48PortCPC13EVENTOUT
49PortCPC14EVENTOUT
50PortCPC15EVENTOUT
51PortDPD0TIM8_CH4NUART4_RXFDCAN1_RXUART9_CTSFMC_D2/FMC_AD2EVENTOUT
52PortDPD1UART4_TXFDCAN1_TXFMC_D3/FMC_AD3EVENTOUT
53PortDPD2TRACED2TIM3_ETRTIM15_BKINUART5_RXSDMMC1_CMDDCMI_D11/PSSI_D11LPTIM4_ETREVENTOUT
54PortDPD3SPI2_SCK/I2S2_CKUSART2_CTS/USART2_NSSFMC_CLKDCMI_D5/PSSI_D5EVENTOUT
55PortDPD4USART2_RTSOCTOSPI1_IO4FMC_NOEEVENTOUT
56PortDPD5TIM1_CH4NSPI2_RDYUSART2_TXFDCAN1_TXOCTOSPI1_IO5FMC_NWEEVENTOUT
57PortDPD6SAI1_D1SPI3_MOSI/I2S3_SDOSAI1_SD_AUSART2_RXOCTOSPI1_IO6SDMMC2_CKFMC_NWAITDCMI_D10/PSSI_D10EVENTOUT
58PortDPD7SPI1_MOSI/I2S1_SDOUSART2_CKOCTOSPI1_IO7SDMMC2_CMDFMC_NE1/FMC_NCELPTIM4_OUTEVENTOUT
59PortDPD8USART3_TXFMC_D13/FMC_AD13EVENTOUT
60PortDPD9USART3_RXFDCAN2_RXFMC_D14/FMC_AD14EVENTOUT
61PortDPD10LPTIM2_CH2USART3_CKFMC_D15/FMC_AD15EVENTOUT
62PortDPD11SAI1_CK1LPTIM2_IN2I2C4_SMBAUSART3_CTS/USART3_NSSUART4_RXOCTOSPI1_IO0SAI2_SD_AFMC_A16/FMC_CLEEVENTOUT
63PortDPD12LPTIM1_IN1TIM4_CH1LPTIM2_IN1I2C4_SCLI3C1_SCLSAI1_D1USART3_RTSUART4_TXOCTOSPI1_IO1SAI2_FS_AFMC_A17/FMC_ALEDCMI_D12/PSSI_D12EVENTOUT
64PortDPD13LPTIM1_CH1TIM4_CH2LPTIM2_CH1I2C4_SDAI3C1_SDAOCTOSPI1_IO3SAI2_SCK_AUART9_RTSFMC_A18DCMI_D13/PSSI_D13LPTIM4_IN1EVENTOUT
65PortDPD14TIM4_CH3UART8_CTSUART9_RXFMC_D0/FMC_AD0EVENTOUT
66PortDPD15TIM4_CH4UART8_RTSUART9_TXFMC_D1/FMC_AD1EVENTOUT
67PortEPE0LPTIM1_ETRTIM4_ETRLPTIM2_CH2LPTIM2_ETRSPI3_RDYUART8_RXFDCAN1_RXSAI2_MCLK_AFMC_NBL0DCMI_D2/PSSI_D2EVENTOUT
68PortEPE1LPTIM1_IN2UART8_TXFDCAN1_TXFMC_NBL1DCMI_D3/PSSI_D3EVENTOUT
69PortEPE2TRACECLKLPTIM1_IN2SAI1_CK1SPI4_SCKSAI1_MCLK_AUSART10_RXUART8_TXOCTOSPI1_IO2ETH_MII_TXD3FMC_A23DCMI_D3/PSSI_D3EVENTOUT
70PortEPE3TRACED0TIM15_BKINSAI1_SD_BUSART10_TXFMC_A19EVENTOUT
71PortEPE4TRACED1SAI1_D2TIM15_CH1NSPI4_NSSSAI1_FS_AFMC_A20DCMI_D4/PSSI_D4EVENTOUT
72PortEPE5TRACED2SAI1_CK2TIM15_CH1SPI4_MISOSAI1_SCK_AFMC_A21DCMI_D6/PSSI_D6EVENTOUT
73PortEPE6TRACED3TIM1_BKIN2SAI1_D1TIM15_CH2SPI4_MOSISAI1_SD_ASAI2_MCLK_BFMC_A22DCMI_D7/PSSI_D7EVENTOUT
74PortEPE7TIM1_ETRUART12_RTSUART7_RXOCTOSPI1_IO4FMC_D4/FMC_AD4EVENTOUT
75PortEPE8TIM1_CH1NUART12_CTS/UART12_NSSUART7_TXOCTOSPI1_IO5FMC_D5/FMC_AD5EVENTOUT
76PortEPE9TIM1_CH1UART12_RXUART7_RTSOCTOSPI1_IO6FMC_D6/FMC_AD6EVENTOUT
77PortEPE10TIM1_CH2NUART12_TXUART7_CTSOCTOSPI1_IO7FMC_D7/FMC_AD7EVENTOUT
78PortEPE11TIM1_CH2SPI1_RDYSPI4_NSSOCTOSPI1_NCSSAI2_SD_BFMC_D8/FMC_AD8EVENTOUT
79PortEPE12TIM1_CH3NSPI4_SCKSAI2_SCK_BFMC_D9/FMC_AD9EVENTOUT
80PortEPE13TIM1_CH3SPI4_MISOSAI2_FS_BFMC_D10/FMC_AD10EVENTOUT
81PortEPE14TIM1_CH4SPI4_MOSISAI2_MCLK_BFMC_D11/FMC_AD11EVENTOUT
82PortEPE15TIM1_BKINTIM1_CH4NUSART10_CKFMC_D12/FMC_AD12EVENTOUT
83PortFPF0I2C2_SDAFMC_A0LPTIM5_CH1EVENTOUT
84PortFPF1I2C2_SCLFMC_A1LPTIM5_CH2EVENTOUT
85PortFPF2LPTIM3_CH2LPTIM3_IN2I2C2_SMBAUART12_TXUSART11_CKFMC_A2LPTIM5_IN1EVENTOUT
86PortFPF3LPTIM3_IN1USART11_TXFMC_A3LPTIM5_IN2EVENTOUT
87PortFPF4LPTIM3_ETRUSART11_RXFMC_A4EVENTOUT
88PortFPF5LPTIM3_CH1I2C4_SCLI3C1_SCLUART12_RXUSART11_CTS/USART11_NSSFMC_A5LPTIM3_IN1EVENTOUT
89PortFPF6TIM16_CH1SPI5_NSSSAI1_SD_BUART7_RXOCTOSPI1_IO3LPTIM5_CH1EVENTOUT
90PortFPF7TIM17_CH1SPI5_SCKSAI1_MCLK_BUART7_TXOCTOSPI1_IO2LPTIM5_CH2EVENTOUT
91PortFPF8TIM16_CH1NSPI5_MISOSAI1_SCK_BUART7_RTSTIM13_CH1OCTOSPI1_IO0LPTIM5_IN1EVENTOUT
92PortFPF9TIM17_CH1NSPI5_MOSISAI1_FS_BUART7_CTSTIM14_CH1OCTOSPI1_IO1LPTIM5_IN2EVENTOUT
93PortFPF10TIM16_BKINSAI1_D3PSSI_D15OCTOSPI1_CLKDCMI_D11/PSSI_D11EVENTOUT
94PortFPF11SPI5_MOSIOCTOSPI1_NCLKSAI2_SD_BFMC_NRASDCMI_D12/PSSI_D12LPTIM6_CH1EVENTOUTADC1_INP2
95PortFPF12FMC_A6LPTIM6_CH2EVENTOUTADC1_INP6/ADC1_INN2
96PortFPF13I2C4_SMBAFMC_A7LPTIM6_IN1EVENTOUTADC2_INP2
97PortFPF14FMC_A8LPTIM6_IN2EVENTOUTADC2_INP6/ADC2_INN2
98PortFPF15I2C4_SDAI3C1_SDAFMC_A9EVENTOUT
99PortGPG0UART9_RXFMC_A10LPTIM4_IN1EVENTOUT
100PortGPG1SPI2_MOSI/I2S2_SDOUART9_TXFMC_A11EVENTOUT
101PortGPG2TIM8_BKINUART12_RXFMC_A12LPTIM6_ETREVENTOUT
102PortGPG3TIM8_BKIN2UART12_TXFMC_A13LPTIM5_ETREVENTOUT
103PortGPG4TIM1_BKIN2FMC_A14/FMC_BA0LPTIM4_ETREVENTOUT
104PortGPG5TIM1_ETRFMC_A15/FMC_BA1EVENTOUT
105PortGPG6TIM17_BKINI3C1_SDAI2C4_SDASPI1_RDYOCTOSPI1_NCSUCPD1_FRSTXFMC_NE3DCMI_D12/PSSI_D12EVENTOUT
106PortGPG7SAI1_CK2I3C1_SCLI2C4_SCLSAI1_MCLK_AUSART6_CKUCPD1_FRSTXFMC_INTDCMI_D13/PSSI_D13EVENTOUT
107PortGPG8TIM8_ETRSPI6_NSSUSART6_RTSETH_PPS_OUTFMC_SDCLKEVENTOUT
108PortGPG9SPI1_MISO/I2S1_SDIUSART6_RXOCTOSPI1_IO6SAI2_FS_BSDMMC2_D0FMC_NE2/FMC_NCEDCMI_VSYNC/PSSI_RDYEVENTOUT
109PortGPG10SPI1_NSS/I2S1_WSSAI2_SD_BSDMMC2_D1FMC_NE3DCMI_D2/PSSI_D2EVENTOUT
110PortGPG11LPTIM1_IN2SPI1_SCK/I2S1_CKUSART10_RXUSART11_RTSSDMMC2_D2ETH_MII_TX_EN/ETH_RMII_TX_ENDCMI_D3/PSSI_D3EVENTOUT
111PortGPG12LPTIM1_IN1PSSI_D15SPI6_MISOUSART10_TXUSART6_RTSSDMMC2_D3ETH_MII_TXD1/ETH_RMII_TXD1FMC_NE4DCMI_D11/PSSI_D11LPTIM5_CH1EVENTOUT
112PortGPG13TRACED0LPTIM1_CH1SPI6_SCKUSART10_CTS/USART10_NSSUSART6_CTS/USART6_NSSSDMMC2_D6ETH_MII_TXD0/ETH_RMII_TXD0FMC_A24LPTIM5_CH2EVENTOUT
113PortGPG14TRACED1LPTIM1_ETRLPTIM1_CH2SPI6_MOSIUSART10_RTSUSART6_TXOCTOSPI1_IO7SDMMC2_D7ETH_MII_TXD1/ETH_RMII_TXD1FMC_A25LPTIM5_IN1EVENTOUT
114PortGPG15SPI4_RDYUSART10_CKUSART6_CTS/USART6_NSSFMC_NCASDCMI_D13/PSSI_D13EVENTOUT
115PortHPH0EVENTOUT
116PortHPH1EVENTOUT
117PortHPH2LPTIM1_IN2OCTOSPI1_IO4SAI2_SCK_BETH_MII_CRSFMC_SDCKE0EVENTOUT
118PortHPH3OCTOSPI1_IO5SAI2_MCLK_BETH_MII_COLFMC_SDNE0EVENTOUT
119PortHPH4I2C2_SCLSPI5_RDYSPI6_RDYPSSI_D14EVENTOUT
120PortHPH5I2C2_SDASPI5_NSSSPI6_RDYFMC_SDNWEEVENTOUT
121PortHPH6TIM1_CH3NTIM12_CH1TIM8_CH1I2C2_SMBASPI5_SCKETH_MII_RXD2FMC_SDNE1DCMI_D8/PSSI_D8EVENTOUT
122PortHPH7TIM1_CH3TIM8_CH1NI2C3_SCLSPI5_MISOETH_MII_RXD3FMC_SDCKE1DCMI_D9/PSSI_D9EVENTOUT
123PortHPH8TIM1_CH2NTIM5_ETRTIM8_CH2I2C3_SDASPI5_MOSIDCMI_HSYNC/PSSI_DEEVENTOUT
124PortHPH9TIM1_CH2TIM12_CH2TIM8_CH2NI2C3_SMBASPI5_NSSDCMI_D0/PSSI_D0EVENTOUT
125PortHPH10TIM1_CH1NTIM5_CH1TIM8_CH3I2C4_SMBASPI5_RDYDCMI_D1/PSSI_D1EVENTOUT
126PortHPH11TIM1_CH1TIM5_CH2TIM8_CH3NI2C4_SCLI3C1_SCLDCMI_D2/PSSI_D2EVENTOUT
127PortHPH12TIM1_BKINTIM5_CH3TIM8_BKINI2C4_SDAI3C1_SDATIM8_CH4NDCMI_D3/PSSI_D3EVENTOUT
128PortHPH13LPTIM1_IN2TIM8_CH1NUART8_TXUART4_TXFDCAN1_TXDCMI_D3/PSSI_D3EVENTOUT
129PortHPH14TIM8_CH2NUART4_RXFDCAN1_RXDCMI_D4/PSSI_D4EVENTOUT
130PortHPH15TIM8_CH3NDCMI_D11/PSSI_D11EVENTOUT
131PortIPI0TIM5_CH4SPI2_NSS/I2S2_WSDCMI_D13/PSSI_D13EVENTOUT
132PortIPI1TIM8_BKIN2SPI2_SCK/I2S2_CKDCMI_D8/PSSI_D8EVENTOUT
133PortIPI2TIM8_CH4SPI2_MISO/I2S2_SDIDCMI_D9/PSSI_D9EVENTOUT
134PortIPI3TIM8_ETRSPI2_MOSI/I2S2_SDODCMI_D10/PSSI_D10EVENTOUT
135PortIPI4TIM8_BKINSPI2_RDYSAI2_MCLK_ADCMI_D5/PSSI_D5EVENTOUT
136PortIPI5TIM8_CH1SAI2_SCK_ADCMI_VSYNC/PSSI_RDYEVENTOUT
137PortIPI6TIM8_CH2SAI2_SD_ADCMI_D6/PSSI_D6EVENTOUT
138PortIPI7TIM8_CH3SAI2_FS_ADCMI_D7/PSSI_D7EVENTOUT
139PortIPI8EVENTOUT
140PortIPI9UART4_RXFDCAN1_RXEVENTOUT
141PortIPI10FDCAN1_RXETH_MII_RX_ERPSSI_D14EVENTOUT
142PortIPI11PSSI_D15EVENTOUT